Graphics processing architecture employing a unified shader

• US 8,760,454 B2
• Filed: 05/17/2011
• Issued: 06/24/2014
• Est. Priority Date: 11/20/2003
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Morein, Stephen L., Lefebvre, Laurent, Gruber, Andrew E., Skende, Andi
• Primary Examiner(s): Tung, Kee M
• Assistant Examiner(s): CHEN, FRANK S
• Application Number:
  US13/109,738
• Publication Number:
  US 20110216077A1
• Time in Patent Office: 1,134 Days
• Field of Search: 345/501
• US Class Current: 345/501
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading

Abstract

A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Claims

1. A method carried out by a unified shader comprising:

performing vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor within the unified shader unless the general purpose register block does not have enough available space therein to store incoming vertex data; and

continuing pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

2. A unified shader, comprising:

a general purpose register block for maintaining data;

a processor unit;

a sequencer, coupled to the general purpose register block and the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in the general purpose register block; and

wherein the processor unit executes instructions that generate a pixel color in response to selected data from the general purpose register block and generates vertex position and appearance data in response to selected data from the general purpose register block.

3. A unified shader comprising:

a processor unit operative to perform vertex calculation operations and pixel calculation operations; and

shared resources, operatively coupled to the processor unit;

the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform pixel calculation operations until enough shared resources become available and then use the shared resources to perform vertex calculation operations.

4. A unified shader comprising:

a processor unit operative to perform vertex calculation operations and pixel calculation operations; and

shared resources, operatively coupled to the processor unit;

the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform vertex calculation operations until enough shared resources become available and then use the shared resources to perform pixel calculation operations.

5. A unified shader comprising:

a processor unit;

a sequencer coupled to the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in a store depending upon an amount of space available in the store.

6. The shader of claim 5, wherein the sequencer further includes circuitry operative to fetch data from a memory.

7. The shader of claim 5, further including a selection circuit operative to provide information to the store in response to a control signal.

8. The shader of claim 5, wherein the processor unit executes instructions that generate a pixel color in response to the selected data.

9. The shader of claim 5, wherein the processor unit generates vertex position and appearance data in response to a selected data.

10. The shader of claim 7, wherein the control signal is provided by an arbiter.

11. A unified shader comprising:

a processor unit flexibly controlled to perform vertex manipulation operations and pixel manipulation operations based on vertex or pixel workload; and

an instruction store and wherein the processor unit of the unified shader performs the vertex manipulation operations and pixel manipulation operations at various degrees of completion based on switching between instructions in the instruction store.