Reduction of inrush current due to voltage sags with switch and shunt resistance

• US 8,766,481 B2
• Filed: 10/14/2011
• Issued: 07/01/2014
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: I-EWM Acquisation, LLC
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Divan, Deepakraj
• Primary Examiner(s): Fleming, Fritz M
• Application Number:
  US13/273,492
• Publication Number:
  US 20120032520A1
• Time in Patent Office: 991 Days
• Field of Search: 307/98, 307/99, 307/103, 307/115, 361/3, 361/8, 361/9, 361/71, 361/58, 323/901, 323/908, 363/49
• US Class Current: 307/103
• CPC Class Codes: H02H 3/025 Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: H02H 9/026 Current limitation using PTC resistors, i.e. resistors with a large positive temperature coefficient

Abstract

Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

Claims

1. A method for the reduction of inrush current to an electrical load that includes a full-wave rectifier due to short-duration voltage sags on an AC input power voltage, comprising the steps of:

providing a current-limiting circuit coupled between the AC input power voltage and an electrical load that includes a full-wave rectifier, the current-limiting circuit comprising a parallel arrangement of (a) a switch comprising a parallel arrangement of (i) a semiconductor switch and (ii) a selectively actuatable relay for providing a conductive pathway between the AC input power voltage and the electrical load, and (b) a shunt resistance that limits the current to the electrical load;

providing a zero crossing detector coupled to receive the input power voltage, the zero crossing detector operative to provide a zero crossing signal to the current-limiting circuit in response to detection of a zero crossing in the AC input power voltage;

providing a sag detector coupled to receive the input power voltage, the sag detector operative to provide a signal to the current-limiting circuit in response to detection of a short-duration sag in the AC input power voltage during steady state operation of the electrical load and to provide an altered signal to the current-limiting circuit in response to detection of the end of the sag in the AC input power voltage and return of the AC input power voltage to a nominal level;

applying the AC input power voltage to the electrical load directly through the selectively actuatable relay in the current-limiting circuit;

in response to the signal from the sag detector, actuating the relay in the current-limiting circuit to disconnect the conductive pathway between the AC input power voltage and the electrical load so as to add the shunt resistance to the electrical load;

subsequent to the sag detector detecting that the AC input power voltage has returned to a nominal voltage, receiving a zero crossing signal from the zero crossing detector at the current-limiting circuit; and

in response to the altered signal from the sag detector and the zero crossing signal from the zero crossing detector, reconnecting the AC input power voltage to the electrical load through the semiconductor switch.

2. The method of claim 1, further comprising the step of timing the reconnecting of the input power voltage to the electrical load after the power voltage has returned to the nominal voltage so as to reduce an occurrence of an inrush current surge flowing to the load.

3. The method of claim 2, wherein the absolute value of the magnitude of the power voltage is less than the magnitude of a rectified voltage across a capacitor associated with a rectifier of the load at a predefined point in the power voltage cycle when reconnecting the input power voltage to the electrical load.

4. The method of claim 1, wherein the power voltage is applied to an inductive load.

5. The method of claim 1, wherein the power voltage is applied to a rectifier capacitor load.

6. The method of claim 1, wherein reconnecting the input power voltage to the load through the semiconductor switch occurs at approximately a zero crossing of the power voltage occurring after the power voltage has returned to the nominal voltage.

7. The method of claim 1, wherein reconnecting the input power voltage to the load through the semiconductor switch occurs at approximately a first one of a plurality of zero crossings occurring after the power voltage has returned to the nominal voltage.

8. The method of claim 1, wherein reconnecting the input power voltage to the load occurs at a point on the power voltage cycle that reduces a differential between an absolute value of a magnitude of the power voltage and a magnitude of a rectified voltage across a capacitor associated with the load to less than or equal to a predefined threshold.

9. The method of claim 1, wherein reconnecting the input power voltage to the load occurs at a point in the power voltage cycle where an absolute value of a magnitude of the power voltage is less than a magnitude of a rectified voltage across a capacitor associated with the load.

10. The method of claim 9, wherein at least one diode in a rectifier employed to convert the power voltage is reverse biased when the absolute value of the magnitude of the power voltage is less than the magnitude of the rectified voltage across the capacitor associated with the load.

11. The method of claim 1, wherein the current-limiting circuit further comprises a gate drive that controls the operation of the semiconductor switch and the relay, wherein the gate drive is operatively coupled to receive the zero crossing signal from the zero crossing detector and the altered signal from the sag detector.

12. The method of claim 11, wherein the gate drive turns on the semiconductor switch in response to receiving the zero crossing signal and subsequent to receiving the altered signal from the sag detector that the voltage sag has ended but prior to actuating the relay for reconnecting the input power voltage to the electrical load.

13. The method of claim 1, wherein the value of the shunt resistance is determined based upon a tradeoff between protection in a multi-load environment and the possibility of nuisance interference with the operation of the load.

14. The method of claim 1, wherein the step of reconnecting the input power voltage to the electrical load further comprises actuating the relay, subsequent to reconnecting the input power voltage to the electrical load through the semiconductor switch.

15. The method of claim 14, wherein the semiconductor switch is turned off subsequent to actuating the relay.

16. The method of claim 1, wherein the conductive pathway provided by the relay presents a path of least resistance for the current flowing to the electrical load.

17. The method of claim 1, wherein the semiconductor switch comprises a thyristor connected in series with a resistance.

18. The method of claim 17, wherein the value of the resistance that is connected in series with the thyristor is less than the value of the shunt resistance.

19. The method of claim 17, wherein the thyristor is in an off state during steady state operation of the load, thereby preventing current from flowing through the resistance that is connected in series with the thyristor.

20. The method of claim 17, wherein the resistance connected in series with the thyristor limits the worst case current that flows to the electrical load through the thyristor to within a maximum rating of the thyristor.

21. The method of claim 1, wherein the shunt resistance does not interfere with operation of the load for sags in the input power voltage that last less than five (5) cycles approximately.

22. The method of claim 1, wherein the shunt resistance is connected in series with a second relay that operates to isolate the electrical load from the input power voltage under sustained overvoltages or undervoltages.

23. The method of claim 22, wherein timing and operation of the second relay is the same as that of the selective-actuatable relay.

24. An apparatus for the reduction of inrush current to an electrical load that includes a full-wave rectifier due to short-duration voltage sags on an AC input power voltage, comprising:

a zero crossing detector coupled to receive the input power voltage and operative to provide a zero crossing signal in response to detection of a zero crossing in the input power voltage;

a sag detector coupled to receive the input power voltage and operative to provide a signal in response to detection of a short-duration sag in the input power voltage applied to the load during a steady-state operation of the load and further operative to provide an altered signal in response to detection of the end of the sag and return of the input power voltage to a nominal level; and

a current-limiting circuit coupled between the input power voltage and the electrical load that includes a full-wave rectifier, the current-limiting circuit comprising a parallel arrangement of (a) a first switch, (b) a semiconductor second switch, and (c) an impedance, the current-limiting circuit responsive to the signal from the sag detector to disconnect the input power voltage from the electrical load though the first switch so as to add the impedance to the load, the current-limiting circuit configured to remove the impedance from the load and reconnect the input power voltage to the electrical load through the semiconductor second switch in response to the zero crossing signal and the altered signal from the sag corrector when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

25. The apparatus of claim 24, wherein the current-limiting circuit includes a gate drive that controls the operation of the semiconductor second switch and the first switch in response to the zero crossing signal from the zero crossing detector and the altered signal from the sag detector.

26. The apparatus of claim 25, wherein the gate drive turns on the semiconductor second switch in response to receiving the zero crossing signal and subsequent to receiving the altered signal from the sag detector indicating that the voltage sag has ended but prior to reconnecting the input power voltage to the load through the first switch.

27. The apparatus of claim 24, wherein the first switch comprises an infinite resistance associated with an open circuit when the first switch is opened.

28. The apparatus of claim 24, wherein the current limiting circuit is configured to time the reconnection of the input power voltage to the load through the semiconductor second switch after the power voltage has returned to the nominal voltage so as to reduce an inrush current surge flowing to the load.

29. The apparatus of claim 28, wherein the current limiting circuit is configured to time the reconnection of the input power voltage to the load through the semiconductor second switch when the absolute value of the magnitude of the power voltage is less than the magnitude of a rectified voltage across a capacitor associated with a rectifier of the load.

30. The apparatus of claim 24, wherein the load is an inductive load.

31. The apparatus of claim 24, wherein the load is a rectifier/capacitor load.

32. The apparatus of claim 24, wherein the current limiting circuit is configured to time the reconnection of the input power voltage to the load at approximately a zero crossing of the power voltage occurring after the power voltage has returned to the nominal voltage.

33. The apparatus of claim 24, wherein the current limiting circuit is configured to time the reconnection of the input power voltage to the load at a point on the power voltage cycle that reduces a differential between an absolute value of a magnitude of the power voltage and a magnitude of a rectified voltage across a capacitor associated with the load to less than or equal to a predefined threshold.

34. The apparatus of claim 24, wherein the semiconductor second switch comprises a thyristor connected in series with a resistance.

35. The apparatus of claim 34, wherein the value of the resistance that is connected in series with the semiconductor second switch is less than the value of the impedance.

36. The apparatus of claim 34, wherein the resistance connected in series with the thyristor limits the worst case current that flows to the electrical load through the thyristor to within a maximum rating of the thyristor.

37. The apparatus of claim 34, wherein the thyristor is in an off state during steady state operation of the load, thereby preventing current from flowing through the resistance that is connected in series with the thyristor.

38. The apparatus of claim 24, wherein the first switch comprises a selectively actuatable relay.

39. The apparatus of claim 24, wherein the input power voltage is reconnected to the load through the semiconductor second switch at approximately a first zero crossing of the power voltage occurring after the power voltage has returned to the nominal voltage.

40. The apparatus of claim 24, wherein the input power voltage is reconnected to the load at approximately a first one of a plurality of zero crossings subsequent to being reconnected through the semiconductor second switch.

41. The apparatus of claim 24, wherein the first switch establishes a direct electrical connection between the input power voltage and the electrical load, thereby presenting a path of least resistance for the current flowing to the electrical load.

42. The apparatus of claim 24, wherein the current-limiting circuit is further configured to reconnect the input power voltage to the electrical load initially through the semiconductor second switch and subsequently through the first switch.

43. The apparatus of claim 24, wherein the shunt resistance is connected in series with a second relay that operates to isolate the electrical load from the input power voltage under sustained overvoltages or undervoltages.

44. The apparatus of claim 43, wherein timing and operation of the second relay is the same as that of the first switch.

45. The apparatus of claim 24, wherein the impedance does not interfere with operation of the load for sags in the input power voltage that last less than five (5) cycles approximately.

46. The apparatus of claim 24, wherein the current-limiting circuit is further configured to reconnect the input power voltage to the electrical load through the first switch and subsequently turn off the semiconductor second switch.

47. The apparatus of claim 24, wherein the value of the impedance is determined based upon a tradeoff between protection in a multi-load environment and the possibility of nuisance interference with the operation of the load.