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Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

  • US 8,774,199 B2
  • Filed: 01/21/2003
  • Issued: 07/08/2014
  • Est. Priority Date: 01/23/1997
  • Status: Expired due to Fees
First Claim
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1. A switch for selectively coupling pairs of nodes on a plurality of fibre channel arbitrated loop (FCAL) nets to each other for one or more simultaneous conversations, comprising:

  • data path circuitry having a plurality of parallel point-to-point transmit/receive channels and multiplexing circuitry to selectively couple individual ones of said transmit/receive channels to transmit-receive terminals;

    a protocol bus;

    a plurality of ports each port for interfacing a local FCAL net to said data path circuitry, each port coupled to said protocol bus, wherein each port includes;

    a serializer/deserializer circuit having terminals for coupling to an FCAL net and having demultiplexing circuitry to convert incoming differential, encoded serial data from said FCAL net to multi-bit characters and having clock recovery circuitry to recover a receive clock therefrom and having multiplexing circuitry for receiving a plurality of multi-bit characters and converting them into a differential, encoded serial data stream;

    an elastic buffer to receive multi-bit characters from and send multi-bit characters to said serializer/deserializer circuit and absorb the differences in transmit and receive rate;

    a routing table memory storing mappings between destination node addresses and port IDs of the port coupled to each destination node;

    a scoreboard means for storing status information; and

    one or more state machine means coupled to said elastic buffer, said routing table memory, said scoreboard means and said protocol bus and at least to said transmit-receive terminals of said data path circuitry for using said routing table memory contents for determining whether destination nodes identified in open primitive signal (OPN) primitives received from source nodes on said local FCAL net are local or remote and using the data content of said scoreboard means to determine if connection to a destination port coupled to said destination node is permissible and transmitting a connection request on said protocol bus to said destination port requesting a connection thereto and using the contents of a connect response frame output by said state machine means of said destination port on said protocol bus for controlling said data path circuitry to implement full duplex connections between said local source and remote destination nodes or to implement full or half duplex connections to remote destination nodes, and for implementing logic and control functions to control said data path circuitry to carry out a dual simplex connections so as to send data and primitives from a source node on said local FCAL net to a remote dual simplex destination node coupled to some other port which is a source node in another half duplex loop tenancy and receive buffer credit flow control primitives back from said dual simplex destination node and to respond to each said buffer credit flow control primitive by transmitting a frame of data to said dual simplex destination node, said state machine means also structured for sending flow control primitives to a third port for transmission to a third node and receive OPN and close primitive signal (CLS) primitives and data frames from said third node when said third port has established a dual simplex connection to a source port through said data path circuitry, and transmit data frames and CLS primitives received from said third node to said source node if and only if said data frames are directed to said source node as indicated by said OPN received from said third node.

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