System and method for increasing die yield

• US 8,775,112 B2
• Filed: 12/18/2003
• Issued: 07/08/2014
• Est. Priority Date: 09/15/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Van Dyke, James M., Montrym, John S., Nagy, Michael B., Treichler, Sean J.
• Primary Examiner(s): Barbee, Manuel L
• Application Number:
  US10/740,723
• Publication Number:
  US 20050251358A1
• Time in Patent Office: 3,855 Days
• Field of Search: 702 81- 84, 702/108, 702117-120, 702/179, 702182-186, 438/4, 438/5, 438/7, 438/10, 438/16, 438/17, 438/24, 438/128, 438/129, 438/130, 438/131, 257/48, 324/500, 324/534, 324/755, 324/763, 700108-110, 716/4
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G05B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

Claims

1. A reduced performance circuit salvage method comprising:

preparing a chip for testing;

testing said chip; and

performing a functional component configuration process on said chip and based upon results of said testing configuring said chip as a reduced performance circuit, wherein tasks are performed at a different performance level in said chip configured as said reduced performance circuit and said chip still be classified as a useful chip, and wherein said functional component configuration process comprises;

receiving art indication of a defective functional component;

determining if said defective functional component is one of a plurality of similar functional components;

disabling said defective functional component if it is one of said plurality of similar functional components;

enabling one or more non-defective functional components; and

providing notification of said disabling and said enabling to a second component other than said defective functional component, wherein said second component is configured to communicate information to at least one of said plurality of similar functional components and bypass said defective functional component to which said second component would otherwise communicate information.

2. The reduced performance circuit salvage method of claim 1 wherein said testing comprises:

identifying a defective functional component;

determining if there is a non-defective functional component included in said integrated circuit, wherein said non-defective functional component performs a similar function as said defective functional component;

designating said defective functional component for non use if said non-defective component is included in said integrated circuit; and

marking said integrated circuit as defective if said non-defective component that perform said similar function in not is included in said integrated circuit.

3. The reduced performance circuit salvage method of claim 1 wherein one of a plurality of homogenous execution components of said chip is disabled or enabled and said disabling said defective functional component results in said chip performing said tasks slower.

4. The reduced performance circuit salvage method of claim 1 further comprising reconfiguring said chip to permit other functional components to perform functions of said disabled functional component at said different performance level, wherein said different performance level corresponds to the number of enabled said non-defective functional components.

5. The reduced performance circuit salvage method of claim 1 wherein said indication of a defective functional component is received from a testing system.

6. A die classification process comprising:

fabricating a plurality of die with similar configurations;

preventing a component from participating in productive contribution within one of said plurality of die without eliminating the ability of said one of said plurality of die to perform a function associated with said component and

classifying said plurality of die in classes based on differentiated performance levels for said functionality, wherein die in said classes are considered useful wherein a first die and a second die included in said plurality of die are included in different products that are sold at different prices in correlation to a performance level at which functionality is provided, and wherein a determination of which manufacturer data sheet information applies to a die included in said plurality of die is not made until after testing is performed.

7. The die classification process of claim 6 wherein said plurality of die are fabricated on a single wafer.

8. The die classification process of claim 6 wherein similar configuration is determined by reviewing manufacturer data sheet information on said plurality of die.

9. The die classification process of claim 6 wherein similar configuration is determined if dies have substantially the same fabrication costs.

10. The die classification process of claim 6 wherein said component is prevented from participating in productive contribution by disabling said component.

11. The die classification process of claim 6 wherein each one of said plurality of dies are fabricated with the same design and are distributed with different performance levels.

12. A die classification process comprising:

fabricating a plurality of die with similar configurations, wherein similar configuration is determined if dies have substantially the same fabrication costs;

preventing a component from participating in productive contribution within one of said plurality of die without eliminating the ability of said one of said plurality of die to perform a function associated with said component; and

classifying said plurality of die based on differentiated performance levels for said functionality, wherein a first die and a second die included in said plurality of die are included in different products that are sold at different prices in correlation to a performance level at witch functionality is provided.

13. The die classification process of claim 12 wherein said component is prevented from participating in productive contribution by disabling said component.

14. The die classification process of claim 12 wherein a determination of which data sheet information applies to a die included in said plurality of die is not made until after testing is performed.

15. The die classification process of claim 12 wherein each one of said plurality of dies are fabricated with the same design and are distributed with different performance levels.

16. The die classification process of claim 12 wherein said one of said plurality of die is reconfigured to permit other functional components to perform functions of said disabled functional component.