Method and apparatus for performing enhanced read and write operations in a FLASH memory system

• US 8,775,772 B2
• Filed: 12/21/2009
• Issued: 07/08/2014
• Est. Priority Date: 08/11/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fuxa, James A., Shelton, Lance W., Haggard, Justin C.
• Primary Examiner(s): Bansal, Gurtej
• Application Number:
  US12/643,688
• Publication Number:
  US 20110040927A1
• Time in Patent Office: 1,660 Days
• Field of Search: 711/202, 711/203, 711/205, 711/209, 711/214, 711/221
• US Class Current: 711/202
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.

Claims

1. A FLASH-based solid state storage system comprising:

a system controller including an external communication bus interface adapted to receive WRITE requests from an external host, where each WRITE request includes a Logical Block Address (LBA) and a page of data to be stored at the LBA;

a volatile memory space accessible to the system controller;

a FLASH memory space containing a plurality of physical address locations, each physical address location being capable of storing a page of data; and

one or more communication buses coupling the system controller to the FLASH memory space,

wherein the system controller is configured to maintain a logical to physical translation table in the volatile memory space, where the logical to physical translation table includes both;

(i) a first group of entries associating a LBA with a physical address location within the FLASH memory space where, for each such entry, data is stored within the physical address location within the FLASH memory space; and

(ii) a second group of entries associating a LBA with one or more data identifiers, each data identifier and each physical address location, respectively, being stored in the logical to physical translation table as a predefined plurality of bits, where;

(a) each such data identifier is associated with a specific data string such that the same data identifier may be associated with two or more distinct LBAs in the second group of entries,

(b) each such data string corresponds to a specific block of data and not to any physical address location within the FLASH memory space; and

(c) no physical address location within the FLASH memory space includes stored data corresponding to any of the specific blocks of data that correspond to a data string; and

wherein the system controller is configured to respond to a WRITE request containing a data string that is associated with a data identifier by storing an entry in the second group of entries and not accessing the FLASH memory space as a result of such WRITE request, and

wherein the system controller is configured to respond to a READ request for data associated with a LBA in the second group of entries by providing a specific data string associated with the data identifier associated with that LBA without accessing the FLASH memory space as a result of the READ request.

2. The FLASH-based solid state storage system of claim 1 wherein the system controller is configured to use a data identifier associated with a data string that is all logical zeros and where no data string stored within the FLASH memory space includes all logical zeros.

3. The FLASH-based solid state storage system of claim 1 wherein the system controller is configured to use a data identifier corresponding to a data string that is all logical ones and where no block of data stored within the FLASH memory space includes all logical ones.

4. The FLASH-based solid state storage system of claim 1 wherein the system controller is configured to monitor the data strings provided in connection with WRITE requests and to assign a data identifier for data strings found to have been included in a predetermined number of WRITE requests.

5. The FLASH-based solid state storage system of claim 1 wherein the volatile memory space is formed from DDR RAM memory devices.

6. The FLASH-based solid state storage system of claim 1 wherein the system controller is configured to compare a representation of data provided to the controller as part of a WRITE request with a representation of the data string associated with a data identifier and, in response to an indication that there is a match between the two representations, creating an entry in the logical to physical translation table associating the LBA received as part of the WRITE request with the data identifier for which such a data string match was identified.

7. The FLASH-based solid state storage system of claim 1 wherein:

(i) the FLASH memory space defines a number of physical address locations, each having a corresponding numeric value; and

(ii) the format of the physical address locations in the logical to physical translation table is the same as the format of the data identifiers.

8. The FLASH-based solid state storage system of claim 1 wherein the system controller maintains a data string cache that associates a separate data identifier with each of the most recent data strings associated with the last N number of WRITE operations, N being a positive integer number, and wherein if a subsequent WRITE operation uses a data string associated with a data identifier in the data string cache, the system controller uses that data identifier as the entry in the logical to physical translation table for that WRITE operation.

9. A method for limiting the number of operations performed on a FLASH memory and of preventing the writing of certain blocks of data into and the reading of certain blocks of data from the FLASH memory, the method comprising the steps of:

(a) receiving a WRITE request including an identification of a logical block address and a block of data corresponding to the block address;

(b) determining whether the received block of data provided in the WRITE request corresponds to a predefined block of data;

(c) if the determination step (b) indicates that the received block of data corresponds to the predefined block of data;

(i) associating the received logical block address with a data identifier composed of a predefined plurality of bits, the data identifier;

(A) not corresponding to a physical address in FLASH memory and (B) providing a representation of the predefined block of data such that the same data identifier may be associated with two or more distinct logical block addresses;

(ii) not writing the predefined block of data to a physical address in the FLASH memory, such that no blocks of data stored within the FLASH memory correspond to the predefined block of data, and

(iii) not accessing the FLASH memory as a result of the received WRITE request;

or

(d) if the determination step (b) indicates that the received block of data does not correspond to the predefined block of data;

associating the received logical block address with a physical address in the FLASH memory and writing the received block of data to the physical address in the FLASH memory;

(e) receiving a READ request including an identification of a logical block address;

(f) determining whether the identification of a logical block address is associated with a data identifier; and

(g) if the determination step (f) indicates that the received identification of a logical block address is associated with a data identifier, returning the predefined block of data and not accessing the FLASH memory as a result of the received READ request.

10. The method of claim 9, wherein the step of determining whether the received block of data corresponds to a predefined block of data involves the step of determining whether the predefined block of data consists of all logical zeros.

11. The method of claim 9 further comprising the steps of:

(a) determining the number of times a given block of data has been stored in the FLASH memory; and

(b) if the determination in step (a) indicates that a given block of data has been stored in the FLASH memory more than a predetermined number of times, associating a data identifier with the given block of data.

12. The method of claim 9 further including the steps of:

maintaining a data string cache in volatile memory including a plurality of entries, at least one of the entries representing a previously received block of data included in a previous WRITE requests that has not been written to a physical address within the FLASH memory;

associating a data identifier with at the least one entry representing the previously received block of data;

determining whether the received block of data provided in the WRITE request corresponds to the previously received block of data; and

if the determination step indicates that the received block of data corresponds to the previously received block of data;

associating the received logical block address with the data identifier associated with the entry representing the previously received block of data and not writing the previously received block of data to a physical address in the FLASH memory, such that no blocks of data stored within the FLASH memory correspond to the predefined block of data.

13. The method of claim 12 wherein the step of maintaining a data string cache includes the steps of storing, in the data string cache, a plurality of entries, each corresponding to a block of data received in one or more previous WRITE requests and wherein the method further includes the steps of:

maintaining a count of the number of times a given block of data was previously received and,

if the count indicates that the given block of data was received more than a predefined number of times, associating a data identifier with the given block of data.

14. A memory system for storing data in one or more FLASH memory devices, the memory system comprising:

a system controller adapted to receive WRITE requests, each WRITE request including a logical address identifier and a set of data; and

a logical to physical translation table accessible to the system controller and stored in volatile RAM memory, the logical to physical translation table including at least;

a first entry associating a first logical address with a physical address in a FLASH memory space;

a second entry associating a second logical address with a data identifier, each data identifier and each physical address, respectively, being stored in the logical to physical translation table as a predefined plurality of bits, where the second logical address is different from the first logical address and wherein the data identifier;

(i) represents a predefined set of data wherein the predefined set of data is not stored within any physical address in the FLASH memory space such that the same data identifier may be associated with two or more distinct logical addresses and (ii) does not correspond to any physical address within the FLASH memory space; and

a third entry associating a third logical address with the data identifier, wherein the third logical address is different from the first and second logical addresses;

wherein the system controller is further adapted to receive a READ request from a host device, the READ request including a logical address identifier, and to return the predefined set of data to the host device without accessing the one or more FLASH memory devices in response to the received READ request if the logical address identifier received in the READ request is one of the second or the third logical addresses.

15. The memory system of claim 14 wherein:

(i) the physical address in the FLASH memory space associated with the first logical address is stored as a data string;

(ii) the data identifier is stored as a data string; and

(iii) the data string for the physical address has the same number of bits as the data string for the data identifier.

16. The memory system of claim 14 further including a volatile memory device coupled to the system controller, wherein the system controller maintains the logical to physical transition table in the volatile memory device.

17. The memory system of claim 14 wherein the predefined set of data represented by the data identifier is a set of data consisting of all logical zeros.

18. The memory system of claim 17 wherein no logical address is associated with a physical address in the FLASH memory space where a data set consisting of all logical zeros is stored.