Multi-cascode amplifier bias techniques

  • US 8,779,859 B2
  • Filed: 08/08/2012
  • Issued: 07/15/2014
  • Est. Priority Date: 08/08/2012
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • multi-cascode bias transistors comprising first and second cascode bias transistors and an input bias transistor, the input bias transistor comprising a drain coupled to the source of the first cascode bias transistor; and

    first and second impedance networks coupled to a first supply voltage for generating bias voltages for the first and second cascode bias transistors, respectively, at least one of the first and second impedance networks comprising a configurable impedance for adjusting at least one bias voltage for the first and second cascode bias transistors;

    wherein the input bias transistor is biased to a gate voltage determined by a reference current through a transistor that is a replica of the input bias transistor.

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