Solid-state thin-film capacitor

• US 8,786,049 B2
• Filed: 07/23/2010
• Issued: 07/22/2014
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Hafezi, Hooman
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US13/260,078
• Publication Number:
  US 20120018844A1
• Time in Patent Office: 1,460 Days
• Field of Search: 257/532, 257/753, 257310-311, 257295-296, 438/780, 361/311, 607/119
• US Class Current: 257/532
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40

Abstract

Solid-state thin-film capacitors are provided. Aspects of the solid-state thin-film capacitors include a first electrode layer of a transition metal, a dielectric layer of an oxide of the transition metal, and a second electrode layer of a metal oxide. Also provided are methods of making the solid-state thin-film capacitors, as well as devices that include the same. The capacitor may have one or more cathodic arc produced structures, i.e., structures produced using a cathodic arc deposition process. The structures may be stress-free metallic structures, porous layers and layers displaying crenulations. Aspects of the invention further include methods of producing capacitive structures using chemical vapor deposition and/or by sputter deposition.

Claims

1. A solid-state thin-film capacitor device comprising:

a semiconductor substrate having a first surface;

a thin-film capacitor comprising a first electrode layer, a dielectric layer and a second electrode layer;

the first electrode layer disposed upon the first surface and comprising a transition metal;

the dielectric layer disposed upon the first electrode layer and comprising an oxide of a transition metal;

the second electrode layer disposed upon the dielectric layer and comprising an oxide of a transition metal, wherein the dielectric layer is disposed between the first electrode layer and the second electrode layer;

wherein the first electrode layer and the second electrode layer are in contact with the dielectric layer, and each layer presents an actual surface area at least two times greater than a surface area defined by an orthogonal length dimension and width dimension of the first surface of the semiconductor substrate;

an electrical circuit element positioned within the semiconductor substrate and enclosed by the semiconductor substrate and the first electrode layer, whereby the thin-film capacitor extends from the first surface of the semiconductor substrate and the electrical circuit element is enclosed by the thin-film capacitor and the semiconductor substrate; and

a hermetic sealing structure disposed about the thin-film capacitor and forming a hermetic seal of the thin-film capacitor in combination with the semiconductor substrate.

2. The device of claim 1, wherein the first electrode layer has an actual surface area greater than 50% of the surface area of the first surface of the semiconductor substrate.

3. The device of claim 1, wherein the first electrode layer, the dielectric layer and the second electrode layer each has an actual surface area of greater than 50% of the surface area of the first surface of the semiconductor substrate.

4. The device of claim 1, wherein the first electrode layer has an actual surface area of greater than 90% of the surface area of the first surface of the semiconductor substrate.

5. The device of claim 1, wherein the first electrode layer, the dielectric layer and the second electrode layer each has an actual surface area of greater than 90% of the surface area of the first surface of the semiconductor substrate.

6. The device of claim 1, wherein the thin film capacitor has a capacitance in the range of from 0.01 microfarads to 0.5 microfarads.

7. The device of claim 1, wherein the hermetic sealing structure further encloses the semiconductor substrate.

8. The device of claim 1, wherein the first electrode layer has an average thickness in the range from 0.1 micrometer to 10 micrometers.

9. The device of claim 1, wherein the dielectric layer has an average thickness in the range from 0.05 micrometer to 1.0 micrometer.

10. The device of claim 1, wherein the second electrode layer has an average thickness in the range from 0.1 micrometer to 10 micrometers.

11. The device of claim 1, wherein the transition metal of the first electrode layer is tantalum, the oxide of the transition metal of the dielectric layer is a tantalum oxide, and the oxide of a transition metal of the second electrode layer is manganese dioxide.

12. The device of claim 1, wherein the first electrode layer and the second electrode layer each presents an actual surface in contact with the dielectric layer greater than a surface area defined by an orthogonal length dimension and width dimension of the first surface of the semiconductor substrate.

13. The device of claim 1, further comprising a second thin-film capacitor, wherein the thin-film capacitor and the second thin-film capacitor are connected in series.

14. The device of claim 1, further comprising a second thin-film capacitor, wherein the thin-film capacitor and the second thin-film capacitor are connected in parallel.

15. The device of claim 1, wherein the capacitor device is comprised within an implantable effector device.

16. The device of claim 1, wherein the capacitor device is comprised within an ingestible event marker.

17. The device of claim 1, wherein the surface of the first electrode layer is a porous surface.

18. The device of claim 1, wherein at least one surface of the device comprises surface crenulations.