Low jitter clock generator for multiple lanes high speed data transmitter

• US 8,786,337 B2
• Filed: 03/14/2013
• Issued: 07/22/2014
• Est. Priority Date: 05/14/2012
• Status: Expired due to Fees

• Current Assignee: Ensphere Solutions, Inc.
• Original Assignee: Ensphere Solutions, Inc.
• Inventors: Mohajeri, Hessam, Tourette, Bruno
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/829,759
• Publication Number:
  US 20130300470A1
• Time in Patent Office: 495 Days
• Field of Search: 327/148, 327/157
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Claims

1. A clock generator circuit comprising:

a master clock generator unit configured to generate a master clock signal; and

a plurality of slave phase locked loop units, each configured to receive the master clock signal as an input reference signal and a corresponding source clock signal,

wherein;

each of the plurality of slave phase locked loop units is a dual loop slave phase lock loop unit that comprises an inner loop and an outer loop, and

the inner loop comprises a frequency synthesizer locked on the master clock signal received from the master clock generator unit.

2. The clock generator circuit of claim 1, wherein the master clock generator unit is a master phase locked loop.

3. The clock generator circuit of claim 1, wherein the master clock generator unit is an LC based oscillator.

4. The clock generator circuit of claim 1, wherein each of the plurality of slave phase locked loop units is fully digital or the phase locked loop is fully digital except the inner loop ring oscillator, charge pump and low-pass filter.

5. The clock generator circuit of claim 1, wherein the plurality of slave phase locked loop units do not comprise any low noise phase locked loops.

6. The clock generator circuit of claim 5, wherein each of the slave phase locked loop units comprises a fractional N synthesizer sub-circuit based on a digital phase rotator.

7. The clock generator circuit of claim 1, wherein the frequency synthesizer comprises a sigma delta fractional N synthesizer and a feedback phase rotator.

8. The clock generator circuit of claim 1, wherein the outer loop controls frequency programming of the inner loop while locking on the corresponding source clock signal.

9. The clock generator circuit of claim 1, wherein the outer loop is fully digital.

10. The clock generator circuit of claim 1, wherein the outer loop has a bandwidth adjustable to depend on the jitter transfer requirements of the system to filter out the jitter from the corresponding source clock signal.

11. The clock generator circuit of claim 1, wherein the outer loop comprises a binary phase detector.

12. The clock generator circuit of claim 11, wherein the binary phase detector comprises a single flip flop.

13. The clock generator circuit of claim 11, wherein output of the binary phase detector goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

14. The clock generator circuit of claim 11, wherein a second phase rotator followed by a divider connects an inner loop output and a binary phase detector input.

15. The clock generator circuit of claim 11, wherein the clock generator is implemented using high density deep sub micron CMOS process technology.