System, method, and computer program product for testing an integrated circuit from a command line

• US 8,789,006 B2
• Filed: 11/01/2012
• Issued: 07/22/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Alfieri, Robert
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/666,842
• Publication Number:
  US 20140123090A1
• Time in Patent Office: 628 Days
• Field of Search: 716/100, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A system, method, and computer program product are provided for testing a circuit representation. A command line input is received at a command line interface. The command line input is translated into one or more test conditions. Additionally, a test environment configured to simulate the circuit representation and verify the one or more test conditions is generated.

Claims

1. A method, comprising:

receiving a command line input at a command line interface, wherein the command line input includes at least one of an assumption and an expression corresponding to a test condition;

translating the command line input into one or more test conditions, wherein based on at least one signal, an assumption specified by the command line input is translated into a command that, when executed, verifies a first test condition corresponding to the assumption; and

generating a test environment configured to simulate a circuit representation and verify the one or more test conditions.

2. The method of claim 1, further comprising:

generating a representation of additional logic specified by the command line input; and

including the representation in the test environment.

3. The method of claim 1, further comprising:

generating a representation of a logic declaration specified by the command line input; and

including the representation in the test environment.

4. The method of claim 3, wherein the representation is a representation of at least one of a register and a counter.

5. The method of claim 1, wherein, a second expression specified by the command line input is translated into a second command that, when executed, verifies a second test condition corresponding to the second expression.

6. The method of claim 5, wherein the circuit representation passes testing when the second test condition is always met during simulation of the circuit representation.

7. The method of claim 5, wherein the circuit representation passes testing when the second test condition is never net during simulation of the circuit representation.

8. The method of claim 5, wherein the circuit representation passes testing when the second test condition is met at least once during simulation of the circuit representation.

9. The method of claim 1, wherein a second expression specified by the command line input is translated into a second command that, when executed, allows at least one output signal or one input signal to have an unknown value during simulation of the circuit representation.

10. The method of claim 1, wherein a second expression specified by the command line input is translated into a second command that, when executed, requires one or more output signals to have known values during simulation of the circuit representation.

11. The method of claim 1, further, comprising:

simulating the circuit representation within the test environment; and

displaying one or more signal traces produced during simulation of the circuit representation in a waveform viewer when the first test condition is met.

12. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

receiving a command line input at a command line interface, wherein the command line input includes at least one of an assumption and an expression corresponding to a test condition;

translating the command line input into one or more test conditions, wherein, based on at least one signal, an assumption specified by the command line input is translated into a command that, when executed, verifies a first test condition corresponding to the assumption; and

generating a test environment configured to simulate a circuit representation and verify the one or more test conditions.

13. The non-transitory computer-readable storage medium of claim 12, the steps further comprising:

generating a representation of additional logic specified by the command line input; and

including the representation in the test environment.

14. The non-transitory computer-readable storage medium of claim 12, the steps further comprising:

generating a representation of a logic declaration specified by the command line input; and

including the representation in the test environment.

15. The non-transitory computer-readable storage medium of claim 12, wherein, based on at least one signal, a second expression specified by the command line input is translated into a second command that, when executed, verifies a second test condition corresponding to the second expression.

16. The non-transitory computer-readable storage medium of claim 12, wherein a second expression specified by the command line input is translated into a second command that, when executed, allows at least one input signal or one output signal to have an unknown value during simulation of the circuit representation.

17. A system for testing a circuit representation, the system comprising:

a memory configured to store program instructions and the circuit representation; and

a processor configured to;

receive a command line input at a command line interface, wherein the command line input includes at least one of an assumption and an expression corresponding to a test condition;

execute one or more of the program instructions to;

translate the command line input into one or more test conditions, wherein, based on at least one signal, an assumption specified by the command line input is translated into a command that, when executed, verifies a first test condition corresponding to the assumption; and

generate a test environment configured to simulate the circuit representation and verify the one or more test conditions.

18. The system of claim 17, wherein the processor is further configured to:

generate a representation of additional logic specified by the command line input; and

include the representation in the test environment.

19. The system of claim 17, wherein the processor is further configured to:

generate a representation of a logic declaration specified by the command line input; and

include the representation in the test environment.

20. A method, comprising:

receiving a command line input at a command line interface, wherein the command line input includes at least one of an assumption and an expression corresponding to a test condition;

translating the command line input into one or more test conditions, wherein an expression specified by the command line input is translated into a command that, when executed, allows at least one input signal or one output signal to have an unknown value during simulation of the circuit representation; and

generating a test environment configured to simulate a circuit representation and verify the one or more test conditions.