Printed, self-aligned, top gate thin film transistor

• US 8,796,125 B2
• Filed: 06/12/2007
• Issued: 08/05/2014
• Est. Priority Date: 06/12/2006
• Status: Expired due to Fees

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Rockenberger, Joerg, Cleeves, James Montague, Kamath, Arvind
• Primary Examiner(s): TORNOW, MARK W
• Application Number:
  US11/818,078
• Publication Number:
  US 20070287237A1
• Time in Patent Office: 2,611 Days
• Field of Search: 438/159, 438/563
• US Class Current: 438/563
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/7866 Non-monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

Claims

1. A method of forming a thin film transistor (TFT), comprising:

a) forming a semiconductor thin film layer;

b) prior to forming a gate electrode of the TFT, printing a doped glass formulation in a pattern on or over the semiconductor thin film layer, the printed doped glass pattern having a gap therein exposing a portion of the semiconductor thin film layer and defining at least one dimension of at least part of the gate electrode;

c) after printing the doped glass pattern, forming the gate electrode in the gap, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and

d) diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

2. The method of claim 1, wherein forming the semiconductor thin film layer comprises printing a liquid-phase ink comprising a semiconductor-containing precursor onto a substrate.

3. The method of claim 1, wherein the doped glass formulation is printed onto or over regions of the semiconductor thin film layer corresponding to source and drain terminals of the TFT.

4. The method of claim 1, comprising printing the doped glass formulation on the semiconductor thin film layer, then forming the gate dielectric film on at least an exposed surface of the semiconductor thin film layer in the gap.

5. The method of claim 1, wherein diffusing the dopant comprises heating the doped glass pattern and the semiconductor thin film layer to a temperature and for a length of time sufficient to form a source/drain structure in the semiconductor thin film layer.

6. The method of claim 1, wherein the step of printing the doped glass formulation comprises printing an ink comprising a doped glass precursor on or over the semiconductor thin film layer, then converting the doped glass precursor ink to a doped glass.

7. The method of claim 1, further comprising removing at least portions of the doped glass pattern, sufficiently to expose surfaces of the semiconductor thin film layer containing diffused dopant.

8. The method of claim 7, wherein removing portions of the doped glass pattern leaves remaining portions of the doped glass pattern.

9. The method of claim 7, further comprising forming a conductive interconnect structure on the exposed surfaces of the semiconductor thin film layer containing diffused dopant.

10. The method of claim 7, further comprising forming an interlayer dielectric film over the doped glass pattern and the gate electrode.

11. The method of claim 1, further comprising forming a passivation layer or a dopant-depleted layer on an exposed surface of the doped glass pattern.

12. A method of forming a thin film transistor (TFT), comprising:

a) forming a semiconductor thin film layer;

b) prior to forming a gate electrode of the TFT, printing doped glass on or over the semiconductor thin film layer in a pattern that forms a gap in the doped glass defining a channel region and a cross-sectional width of at least part of the gate electrode;

c) after printing the doped glass in the pattern, forming the gate electrode on or over the channel region and in the gap, the gate electrode comprising a gate dielectric film and a gate conductor thereon;

d) diffusing a dopant from the doped glass pattern into the semiconductor thin film layer;

e) forming a patterned interlayer dielectric film over the doped glass pattern and the gate electrode, the patterned interlayer dielectric film having an exposed upper surface; and

f) etching the doped glass pattern using the exposed patterned interlayer dielectric film as a mask.

13. The method of claim 12, wherein etching the doped glass pattern exposes surfaces of the semiconductor thin film layer containing diffused dopant.

14. The method of claim 13, wherein etching the doped glass pattern leaves remaining portions of the doped glass pattern.

15. The method of claim 13, further comprising forming a conductive interconnect structure on the exposed surfaces of the semiconductor thin film layer containing diffused dopant.

16. The method of claim 15, wherein forming the conductive interconnect structure comprises printing an ink containing a metal precursor and converting the metal precursor to a metal.

17. The method of claim 15, further comprising printing a second interlayer dielectric film over exposed active areas.

18. The method of claim 12, wherein forming the semiconductor thin film layer comprises printing a liquid-phase ink comprising a semiconductor-containing precursor onto a substrate and converting the semiconductor-containing precursor to the semiconductor thin film.

19. The method of claim 18, wherein the semiconductor-containing precursor comprises a silane or silicon nanoparticles.

20. The method of claim 12, wherein forming the patterned interlayer dielectric film comprises printing an ink containing a dielectric precursor and converting the dielectric precursor to the patterned interlayer dielectric film.

21. The method of claim 12, wherein the etching step comprises wet etching exposed surfaces of the doped glass pattern with a HF-based wet etchant.

22. The method of claim 12, wherein the doped glass pattern is printed onto or over regions of the semiconductor thin film layer corresponding to source and drain terminals of the TFT.

23. The method of claim 12, comprising printing the doped glass pattern on the semiconductor thin film layer, then forming the gate dielectric film on at least an exposed surface of the semiconductor thin film layer in the gap.

24. The method of claim 12, wherein diffusing the dopant comprises heating the doped glass pattern and the semiconductor thin film layer to a temperature and for a length of time sufficient to form a source/drain structure in the semiconductor thin film layer.

25. The method of claim 12, wherein the step of printing the doped glass pattern comprises printing an ink comprising a doped glass precursor on or over the semiconductor thin film layer, then converting the doped glass precursor to a doped glass.

26. A method of forming a thin film transistor (TFT), comprising:

a) forming a semiconductor thin film layer;

b) forming a gate dielectric film on an entire surface of the semiconductor thin film layer;

c) prior to forming a gate electrode of the TFT, printing a doped glass formulation in a pattern on or over the gate dielectric film, in a manner leaving a gap in the doped glass pattern exposing a portion of the gate dielectric film and defining a channel region and at least one dimension of at least part of the gate electrode;

d) after printing the doped glass pattern, forming the gate electrode in the gap, the gate electrode filling a width of the gap and comprising the gate dielectric film and a gate conductor thereon; and

e) diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

27. The method of claim 26, comprising forming the gate conductor on the gate dielectric film, at least in the gap.

28. The method of claim 27, wherein forming the gate conductor comprises printing an ink comprising a gate conductor precursor on the gate dielectric film.