Method and system of exchanging information between processors

• US 8,799,706 B2
• Filed: 01/25/2005
• Issued: 08/05/2014
• Est. Priority Date: 03/30/2004
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Bruckert, William F., Garcia, David J., Heynemann, Thomas A., Klecka, James S., Sprouse, Jeffrey A.
• Primary Examiner(s): Lottich, Joshua P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US11/042,985
• Publication Number:
  US 20050246578A1
• Time in Patent Office: 3,479 Days
• Field of Search: 714/9, 714/11, 714/12, 714/13, 712/27
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling

Abstract

A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

Claims

1. A method comprising:

exchanging information between a plurality of processors comprising

writing, by a first processor, a first datum to a logic device, and then continuing processing of a user program by the first processor;

writing, by a second processor, a second datum to the logic device, and then continuing processing of a user program by the second processor;

making a determination, by the logic device, that both the first and second processors have written their respective datum to the logic device; and

triggered by the determination

writing, by the logic device, the first and second datum to each of the first and second processors.

2. The method as defined in claim 1 further comprising:

wherein writing by the first processor further comprises writing to a first memory location of the logic device;

wherein writing by the second processor further comprises writing to a second memory location of the logic device; and

wherein writing by the logic device further comprises writing the first and second datum to a memory of the first processor and writing the first and second datum to a memory of the second processor.

3. The method as defined in claim 2 wherein writing by the logic device further comprises writing a time of day value to the memory of the first processor, and writing the time of day value to the memory of the second processor.

4. The method as defined in claim 1 further comprising:

writing, by a third processor, a third datum to the logic device, and then continuing processing of a user program by the third processor;

wherein writing by the logic device further comprises writing each of the first, second and third datum to each of the processors.

5. The method as defined in claim 4 further comprising:

wherein writing by the first processor further comprises writing to a first memory location of the logic device;

wherein writing by the second processor further comprises writing to a second memory location of the logic device;

wherein writing by the third processor further comprises writing to a third memory location of the logic device;

wherein writing by the logic device further comprises writing each of the first, second and third datum to the memory of each of the first, second and third processor.

6. The method as defined in claim 5 wherein writing by the logic device further comprises writing a time of day value to the memory of each of the first, second and third processor.

7. The method as defined in claim 1 further comprising:

wherein writing by the a first processor further comprises writing the first datum to the logic device, and then continuing processing by the first processor without stalling the first processor between writing the first datum and continuing processing; and

wherein writing by the second processor further comprises writing the second datum to the logic device, and then continuing processing by the second processor without stalling the second processor between writing the second datum and continuing processing.