Wireless communication receiver, a wireless communication receiving method and a television receiver

• US 8,804,049 B2
• Filed: 01/31/2008
• Issued: 08/12/2014
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Yang, Shun-An
• Primary Examiner(s): Lee, Michael
• Application Number:
  US12/865,398
• Publication Number:
  US 20100321586A1
• Time in Patent Office: 2,385 Days
• Field of Search: 348/725, 348731-733, 348553-570, 348714-716, 370/509, 370/203, 370/208, 375/259, 375/260
• US Class Current: 348/726
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42692 for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/6131 involving transmission via a mobile phone network wireless downlink channel access H04W74/006

Abstract

The present invention relates to a wireless communication receiver, wireless communication receiving method and television receiver. The wireless communication receiver has signal processing circuits including a first signal processing circuit and a second signal processing circuit, a data storage module, and a deinterleaver. The first signal processing circuit receives a wireless communication signal and then performs a first signal processing to generate a first output data according to the wireless communication signal. The deinterleaver stores the first output data into the data storage module, and retrieves a deinterleaved data corresponding to the first output signal from the data storage module. The second signal processing circuit performs a second signal processing to generate a second output data according to the deinterleaved data. The data storage module is shared by the deinterleaver and at least one of the signal processing circuits for data storage, thereby effectively reducing the production cost.

Claims

1. A wireless communication receiver, comprising:

a data storage module;

a deinterleaver, coupled to the data storage module, for storing a first output data into the data storage module, and retrieving a deinterleaved data corresponding to the first output data from the data storage module; and

a plurality of signal processing circuits, comprising;

a first signal processing circuit, coupled to the deinterleaver, for receiving a wireless communication signal, and generating the first output data by performing a first signal processing operation according to the wireless communication signal, wherein the first signal processing circuit comprises;

a signal receiving circuit for receiving the wireless communication signal and accordingly generating a received signal;

a channel estimation/equalization circuit for generating a channel estimation/equalization output by performing a channel estimation/equalization according to the received signal; and

a channel state information generation circuit for generating a channel state information, wherein the first output data includes the channel estimation/equalization output and the channel state information; and

a second signal processing circuit, coupled to the deinterleaver, for generating a second output data by performing a second signal processing operation according to the deinterleaved data;

wherein the data storage module is shared by the deinterleaver and the second signal processing circuit for data storage, and the deinterleaver is further coupled to the channel estimation/equalization circuit and the channel state information generation circuit, and utilized for storing the channel estimation/equalization output and the channel state information into the data storage module, respectively, and retrieving a deinterleaved data corresponding to the channel estimation/equalization output and a deinterleaved data corresponding to the channel state information from the data storage module, respectively.

2. The wireless communication receiver of claim 1, wherein the wireless communication signal is an orthogonal frequency division multiplexing (OFDM) signal.

3. The wireless communication receiver of claim 1, wherein the wireless communication signal is a digital television signal.

4. The wireless communication receiver of claim 3, wherein the digital television signal complies with a digital television standard defined by People'"'"'s Republic of China (P.R.C.).

5. The wireless communication receiver of claim 1, wherein the first output data is a soft decision output.

6. The wireless communication receiver of claim 5, wherein the first signal processing circuit further comprises:

a demapping circuit, for generating a demapping output according to the received signal;

and

a multiplier, coupled to the demapping circuit, the channel state information generation circuit, and the deinterleaver, for generating the first output data to the deinterleaver according to the demapping output and the channel state information.

7. The wireless communication receiver of claim 1, further comprising:

a data buffer module, coupled between the data storage module and the deinterleaver, for buffering data transmitted between the data storage module and the deinterleaver;

wherein the data buffer module and the deinterleaver are both disposed inside a chip, and the data storage module is disposed outside of the chip.

8. The wireless communication receiver of claim 7, wherein the data buffer module comprises:

an input buffer, for continuously writing buffered data in the input buffer into the data storage buffer when a data amount of the buffered data in the input buffer reaches a predetermined value; and

an output buffer, for continuously buffering data read from the data storage module until a data amount of buffered data in the output buffer reaches a predetermined value.

9. The wireless communication receiver of claim 7, wherein the first output data corresponds to a first bit width, the data buffer module and the data storage module transmit data therebetween according to a second bit width, and the first bit width is different from the second bit width.

10. The wireless communication receiver of claim 9, wherein data that is buffered in the data buffer module and corresponds to the first output data has a third bit width less than the first bit width.

11. The wireless communication receiver of claim 1, wherein the deinterleaver is utilized for performing a convolutional deinterleaving operation;

the data storage module includes a plurality of data buffer blocks corresponding to a plurality of deinterleaving branches, respectively; and

buffer lengths of the data buffer blocks are greater than minimum buffer lengths required by the corresponding deinterleaving branches involved in performing the convolutional deinterleaving operation, respectively.

12. A wireless communication receiving method, comprising:

performing a first signal processing operation for receiving a wireless communication signal and generating a first output data according to the wireless communication signal;

performing a deinterleaving operation for storing the first output data into a data storage module and retrieving a deinterleaved data corresponding to the first output data from the data storage module; and

performing a second signal processing operation for generating a second output data according to the deinterleaved data;

wherein the data storage module is shared by the deinterleaving operation and the second signal processing operation for data storage, and the first signal processing operation comprises;

receiving the wireless communication signal and accordingly generating a received signal;

generating a channel state information; and

generating a channel estimation/equalization output by performing a channel estimation/equalization according to the received signal, wherein the first output data includes the channel estimation/equalization output and the channel state information, and the deinterleaving operation stores the channel estimation/equalization output and the channel state information into the data storage module, respectively, and retrieves a deinterleaved data corresponding to the channel estimation/equalization output and a deinterleaved data corresponding to the channel state information from the data storage module, respectively.

13. The wireless communication receiving method of claim 12, wherein the wireless communication signal is an orthogonal frequency division multiplexing (OFDM) signal.

14. The wireless communication receiving method of claim 12, wherein the wireless communication signal is a digital television signal.

15. The wireless communication receiving method of claim 14, wherein the digital television signal complies with a digital television standard defined by People'"'"'s Republic of China (P.R.C.).

16. The wireless communication receiving method of claim 12, wherein the first output data is a soft decision output.

17. The wireless communication receiving method of claim 16, the first signal processing operation further comprises:

generating a demapping output according to the received signal;

and

generating the first output data according to a product of the demapping output and the channel state information.

18. The wireless communication receiving method of claim 12, further comprising:

providing a data buffer module, and utilizing the data buffer module for buffering the first output data generated from the deinterleaving operation to the data storage module and buffering the deinterleaved data read from the data storage module;

wherein the first output data corresponds to a first bit width, the data buffer module and the data storage module transmit data therebetween according to a second bit width, and the first bit width is different from the second bit width.

19. The wireless communication receiving method of claim 18, wherein data that is buffered in the data buffer module and corresponds to the first output data has a third bit width less than the first bit width.

20. The wireless communication receiving method of claim 12, wherein the deinterleaving operation is a convolutional deinterleaving operation;

the data storage module includes a plurality of data buffer blocks corresponding to a plurality of deinterleaving branches, respectively; and

buffer lengths of the data buffer blocks are greater than minimum buffer lengths required by the corresponding deinterleaving branches involved in performing the convolutional deinterleaving operation, respectively.

21. A wireless communication receiver, comprising:

a data storage module;

a memory bus, coupled to the data storage module;

a deinterleaver, coupled to the data storage module, for storing a first output data into the data storage module, and retrieving a deinterleaved data corresponding to the first output data from the data storage module; and

a plurality of signal processing circuits, comprising;

a first signal processing circuit, coupled to the deinterleaver, for receiving a wireless communication signal and generating the first output data by performing a first signal processing operation according to the wireless communication signal, wherein the first signal processing circuit comprises;

a signal receiving circuit for receiving the wireless communication signal and accordingly generating a received signal;

a channel estimation/equalization circuit for generating a channel estimation/equalization output by performing a channel estimation/equalization according to the received signal; and

a channel state information generation circuit for generating a channel state information, wherein the first output data includes the channel estimation/equalization output and the channel state information; and

a second signal processing circuit, coupled to the deinterleaver, for generating a second output data by performing a second signal processing operation according to the deinterleaved data;

wherein the deinterleaver and the second signal processing circuit access the data storage module via the memory bus, and the deinterleaver is further coupled to the channel estimation/equalization circuit and the channel state information generation circuit, and utilized for storing the channel estimation/equalization output and the channel state information into the data storage module, respectively, and retrieving a deinterleaved data corresponding to the channel estimation/equalization output and a deinterleaved data corresponding to the channel state information from the data storage module, respectively.

22. The wireless communication receiver of claim 21, wherein the first output data is a soft decision output.

23. The wireless communication receiver of claim 21, further comprising:

a memory controller, for arbitrating an access right of the memory bus requested by the deinterleaver and the at least one of the signal processing circuits.

24. The wireless communication receiver of claim 21, further comprising:

a data buffer module, coupled between the data storage module and the deinterleaver, for buffering data transmitted between the data storage module and the deinterleaver;

wherein the first output data corresponds to a first bit width, the memory bus has a second bit width, and the first bit width is different from the second bit width.

25. The wireless communication receiver of claim 24, wherein data that is buffered in the data buffer module and corresponds to the first output data has a third bit width less than the first bit width.

26. A television receiver, comprising:

a data storage module;

a demodulator, for receiving and demodulating a digital television signal and accordingly generating a bit stream, the demodulator comprising;

a first signal processing circuit, for generating a first output data by performing a first signal processing operation according to the digital television signal,

wherein the first signal processing circuit comprises;

a signal receiving circuit for receiving the digital television signal and accordingly generating a received signal;

a channel estimation/equalization circuit for generating a channel estimation/equalization output by performing a channel estimation/equalization according to the received signal; and

a channel state information generation circuit for generating a channel state information, wherein the first output data includes the channel estimation/equalization output and the channel state information; and

a deinterleaver, coupled to the first signal processing circuit and the data storage module, for storing the first output data into the data storage module and retrieving a deinterleaved data corresponding to the first output data from the data storage module;

an error-correction decoding module, coupled to the deinterleaver, for performing an error-correction decoding operation according to the deinterleaved data; and

a descrambler, coupled to the error-correction decoding module, for generating the bit stream by performing a descrambling operation according to an output of the error-correction decoding module; and

a backend decoder, coupled to the demodulator, for receiving and decoding the bit stream;

wherein the data storage module is shared by the deinterleaver and the backend decoder for data storage, and the deinterleaver is further coupled to the channel estimation/equalization circuit and the channel state information generation circuit, and utilized for storing the channel estimation/equalization output and the channel state information into the data storage module, respectively, and retrieving a deinterleaved data corresponding to the channel estimation/equalization output and a deinterleaved data corresponding to the channel state information from the data storage module, respectively.

27. The television receiver of claim 26, wherein the first signal processing circuit further comprises:

a demapping circuit, for generating a demapping output according to the received signal;

and

a multiplier, coupled to the demapping circuit, the channel state information generation circuit, and the deinterleaver, for generating the first output data to the deinterleaver according to the demapping output and the channel state information.

28. The television receiver of claim 26, wherein the error-correction decoding module comprises:

a low-density parity-check (LDPC) decoder, coupled to the deinterleaver, for generating an LDPC decoding output by performing an LDPC decoding operation according to the deinterleaved data; and

a Bose-Chaudhuri-Hocquengham (BCH) decoder, coupled to the LDPC decoder, for generating a BCH decoding output by performing a BCH decoding operation according to the LDPC decoding output, wherein the descrambler generates the bit stream by performing the descrambling operation upon the BCH decoding output.

29. The television receiver of claim 26, wherein the first output data is a soft decision output.

30. The television receiver of claim 26, wherein the digital television signal complies with a digital television standard defined by People'"'"'s Republic of China (P.R.C.).

31. The television receiver of claim 26, further comprising:

a data buffer module, coupled between the data storage module and the deinterleaver, for buffering data transmitted between the data storage module and the deinterleaver;

wherein the data buffer module and the deinterleaver are both disposed inside a chip, and the data storage module is disposed outside of the chip.

32. The television receiver of claim 31, wherein the data buffer module comprises:

an input buffer, for continuously writing buffered data in the input buffer into the data storage buffer when a data amount of the buffered data in the input buffer reaches a predetermined value; and

an output buffer, for continuously buffering data read from the data storage module until a data amount of buffered data in the output buffer reaches a predetermined value.

33. The television receiver of claim 31, wherein the first output data corresponds to a first bit width, the data buffer module and the data storage module transmit data therebetween according to a second bit width, and the first bit width is different from the second bit width.

34. The television receiver of claim 31, wherein data that is buffered in the data buffer module and corresponds to the first output data has a third bit width less than the first bit width.