Normally-off III-nitride metal-2DEG tunnel junction field-effect transistors

• US 8,809,987 B2
• Filed: 09/08/2010
• Issued: 08/19/2014
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Hong Kong University of Science and Technology
• Original Assignee: Hong Kong University of Science and Technology
• Inventors: Chen, Jing, Yuan, Li, Chen, Hongwei, Zhou, Chunhua
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/699,296
• Publication Number:
  US 20130092958A1
• Time in Patent Office: 1,441 Days
• Field of Search: 257/76, 257/77, 257/194, 257/472, 438/172, 438/534, 438/572
• US Class Current: 257/472
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]

Abstract

Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.

Claims

1. A tunnel junction field-effect transistor (TJ-FET) having a source, a gate, and a drain, the TJ-FET comprising:

a substrate comprising a buffer layer deposited on the substrate and a barrier layer deposited on the buffer layer, the buffer layer and the barrier layer forming a heterojunction of the TJ-FET at an interface of the buffer layer and the barrier layer; and

a metal region at the source, adjacent to the buffer layer, and spanning across the interface, wherein the metal region forms a gate-controlled Schottky tunnel junction with the heterojunction.

2. The TJ-FET of claim 1, the substrate comprising at least one of sapphire, silicon (111), silicon carbide (SiC), aluminum nitride (AlN), or GaN.

3. The TJ-FET of claim 1, the buffer layer is deposited on the substrate over a nucleation layer comprised of a group III-nitride.

4. The TJ-FET of claim 1, the substrate comprises sapphire, the buffer layer comprises undoped GaN, and the barrier layer comprises a III-nitride barrier layer.

5. The TJ-FET of claim 1, further comprising:

an insulating dielectric layer deposited above the barrier layer proximate to the gate.

6. The TJ-FET of claim 5, further comprising:

the gate deposited above the insulating dielectric layer.

7. The TJ-FET of claim 6, the gate further adapted to partially overlay a portion of the metal region that is electrically isolated from the metal region by the insulating dielectric layer.

8. The TJ-FET of claim 7, the gate further adapted to at least partially fill a trench etched in a portion of the barrier layer.

9. The TJ-FET of claim 1, the heterojunction comprising a two-dimensional electron gas (2DEG) conducting channel proximate to the gate, wherein the gate-controlled Schottky tunnel junction of the TJ-FET is adapted to produce a tunneling current in response to a voltage applied to the gate.

10. The TJ-FET of claim 9, further comprising:

the drain spanning a portion of the heterojunction and in at least one of ohmic contact or Schottky contact with the 2DEG.

11. A normally-off metal two-dimensional electron gas (metal-2DEG) tunnel junction field-effect transistor (TJ-FET), comprising:

a second nitride semiconductor layer deposited on a first nitride semiconductor layer;

a nitride semiconductor barrier layer deposited on the second nitride semiconductor layer and forming a heterojunction comprising a two-dimensional electron gas (2DEG) at an interface of the nitride semiconductor barrier layer and the second nitride semiconductor layer; and

at least one metallic source contact associated with the metal-2DEG TJ-FET and in Schottky contact with the 2DEG across the heterojunction, wherein the at least one metallic source contact is adapted to produce a tunneling current between the at least one metallic source contact and the 2DEG in response to a voltage applied to a gate of the metal-2DEG TJ-FET.

12. The metal-2DEG TJ-FET of claim 11, further comprising at least one of an ohmic or a Schottky drain contact electrically coupled to the at least one metallic source contact across the heterojunction.

13. A method of forming a tunnel junction field-effect transistor (TJ-FET) having at least one design location for a source, a gate, and a drain of the TJ-FET, the method comprising:

depositing a buffer layer over a substrate;

depositing a barrier layer over the buffer layer to form a heterojunction of the TJ-FET comprising a two-dimensional electron gas (2DEG); and

forming a tunnel junction to the 2DEG comprising forming a metallic Schottky source contact in direct physical contact to the 2DEG across the heterojunction.

14. The method of claim 13, the depositing the buffer layer includes growing the buffer layer over at least one of a sapphire substrate, a silicon (111) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Gallium Nitride (GaN) substrate.

15. The method of claim 13, the depositing the buffer layer includes growing the buffer layer over the substrate having a III-nitride nucleation layer.

16. The method of claim 13, further comprising:

trenching a portion of the barrier layer proximate to the design location for the gate.

17. The method of claim 13, further comprising:

growing a gate insulating dielectric layer above the barrier layer proximate to the design location for the gate.

18. The method of claim 17, further comprising:

forming a metallic gate over the gate insulating dielectric layer to partially overlay a portion of the metallic Schottky source contact.

19. The method of claim 13, further comprising:

forming a drain contact in at least one of ohmic contact or Schottky contact with the 2DEG.

20. The method of claim 19, the forming a drain contact includes electrically coupling the drain contact to the metallic Schottky source contact across the heterojunction.