System and method for high speed packet transmission

• US 8,811,390 B2
• Filed: 10/29/2009
• Issued: 08/19/2014
• Est. Priority Date: 05/15/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai
• Primary Examiner(s): Pham, Brenda H
• Application Number:
  US12/608,972
• Publication Number:
  US 20100061393A1
• Time in Patent Office: 1,755 Days
• Field of Search: 370/360, 370/363, 370/365, 370/389, 370/368, 370/371, 370/374, 370/381, 370/395.7, 370/395.71, 370/419, 370/428, 370/423, 370/463, 370/474, 370/359, 370/396, 370/395.6
• US Class Current: 370/359
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04Q 11/0428 Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Abstract

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Claims

1. A system for data transmission comprising:

a first integrated circuit (IC) with a plurality of cores, wherein each said core is operative to provide a bi-directional pipeline for packets corresponding to a given one of a plurality of media access control (MAC) interfaces, each said core is further operative to receive packets from and dispatch packets to at least one memory structure, each said core comprises a local switching circuit to transfer packets between the core and at least one other of the cores, and the first IC comprises a backplane transmit sorter circuit that controls dispatch of packets from the plurality of cores to their intended destinations.

2. The system of claim 1 further comprising:

the plurality of MAC interfaces for facilitating receipt and transmission of packets over an associated set of physical interfaces; and

second and third ICs coupled to the plurality of MAC interfaces and the at least one memory structure, each of the second and third ICs configured to;

perform initial processing of packets received from a respective associated MAC interface of the plurality of MAC interfaces,

schedule the transmission of packets to the respective associated MAC interface, and

dispatch and retrieve packets to and from the at least one memory structure.

3. The system of claim 1 wherein the at least one memory structure is a quad data rate (QDR) memory module.

4. The system of claim 1 wherein the first IC is a field programmable gate array (FPGA).

5. The system of claim 1 wherein the local switching circuit of each said core of the plurality of cores of the first IC comprises a FIFO.

6. The system of claim 1 wherein each said core of the plurality of cores of the first IC comprises a transmit quality of service module circuit operative to determine an order in which packets received at the said core from a backplane and the local switching circuit are transmitted to the at least one memory structure.

7. The system of claim 1 wherein the backplane transmit sorter circuit implements a number of FIFOs to organize packets prior to transmission to one or more slots on a backplane.

8. The system of claim 7 wherein the backplane transmit sorter circuit implements a number of FIFOs equal to a number of slots on the backplane.

9. The system of claim 1 wherein the first IC comprises a receive FIFO arbiter circuit operative to arbitrate the receipt of data from the plurality of cores of the first IC for placement in one or more receive FIFOs.

10. The system of claim 1 wherein the first IC comprises a backplane transmit grouper circuit operative to modify a size of a data packet for transmission over a backplane.