Nonvolatile memory systems with embedded fast read and write memories

• US 8,817,537 B2
• Filed: 08/15/2013
• Issued: 08/26/2014
• Est. Priority Date: 10/24/2007
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Greenthread Limited
• Inventors: Rao, G. R. Mohan
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/967,649
• Publication Number:
  US 20140071752A1
• Time in Patent Office: 376 Days
• Field of Search: 365/185.08, 365/185.11, 365/185.12, 711/E12.008, 711/103, 711/E12.001
• US Class Current: 365/185.08
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G11C 11/02 using magnetic elements
• CPC Class Codes: G11C 11/225 Auxiliary circuits
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Claims

1. A memory system comprising:

a non-volatile memory organized to include a plurality of blocks each having a plurality of pages;

a volatile memory ;

a first buffer capable of temporarily storing at least one page;

a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said non-volatile memory, said one or more portions being less than the entirety of said page;

said system adapted to locate said page associated with said one or more write requests in said non-volatile memory, and to selectively write said page to said first buffer;

said system further adapted to locate in said first buffer said one or more portions of said page associated with said one or more write requests, and to selectively write said one or more portions to said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;

said system further adapted to write said one or more changes from said second buffer to said volatile memory, thereby updating said one or more portions associated with said one or more write requests to include said one or more changes; and

said system further adapted to write said one or more updated portions from said volatile memory to said first buffer, thereby updating said page stored therein to include said one or more changes associated with said one or more write requests.

2. A memory system as defined in claim 1 wherein said non-volatile memory comprises a NAND flash memory.

3. A memory system as defined in claim 1 wherein said non-volatile memory comprises a multi-level cell (MLC) NAND flash memory.

4. The memory system as defined in claim 1 wherein said non-volatile memory comprises one of (i) a magnetic RAM, (ii) a resistive RAM, (iii) a ferroelectric memory, (iv) a nanotube memory and (v) a phase change memory.

5. A memory system as defined in claim 1 wherein said volatile memory comprises one of (i) a dynamic random access memory (DRAM) and (ii) a static random access memory (SRAM).

6. The memory system as defined in claim 1 wherein said first buffer comprises a static random access memory (SRAM).

7. A flash memory system comprising:

a NAND flash memory organized to include a plurality of blocks each having a plurality of pages;

a volatile memory;

a controller;

a first buffer capable of temporarily storing at least one page;

a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said NAND flash memory, said one or more portions being less than the entirety of said page;

said controller locating said page associated with said one or more write requests in said NAND flash memory, and selectively writing said page from said NAND flash memory to said first buffer;

said controller further locating in said first buffer said one or more portions of said page associated with said one or more write requests, and selectively writing said one or more portions to said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;

said controller further writing said one or more changes from said second buffer to said volatile memory, thereby updating said one or more portions associated with said one or more write requests to include said one or more changes; and

said controller further writing said one or more updated portions from said volatile memory to said first buffer, thereby updating said page stored therein to include said one or more changes associated with said one or more write requests.

8. A flash memory system as defined in claim 7 wherein said NAND flash memory comprises a multi-level cell (MLC) NAND flash memory.

9. A flash memory system as defined in claim 7 wherein said non-volatile memory comprises one of (i) a magnetic RAM, (ii) a resistive RAM, (iii) a ferroelectric memory, (iv) a nanotube memory and (v) a phase change memory.

10. A flash memory system as defined in claim 7 wherein said volatile memory comprises one of (i) a dynamic random access memory (DRAM) and (ii) a static random access memory (SRAM).

11. A flash memory system as defined in claim 7 wherein said first buffer comprises a static random access memory (SRAM).

12. In a memory system which includes a non-volatile memory organized to include a plurality of blocks each having a plurality of pages, a volatile memory, a first buffer capable of temporarily storing at least one page, and a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said non-volatile memory, said one or more portions being less than the entirety of said page, the method for writing said one or more changes requested by said one or more write requests to one or more portions of a page in said non-volatile memory, comprising the steps of:

receiving in said second buffer information associated with said one or more write requests;

locating in said non-volatile memory said page associated with said one or more write requests;

selectively writing said located page to said first buffer;

locating in said first buffer said one or more portions of said page associated with said one or more write requests;

selectively writing said one or more portions to said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;

writing said one or more changes from said second buffer to said volatile memory, thereby updating said one or more portions associated with said one or more write requests to include said one or more changes; and

writing said one or more updated portions from said volatile memory to said first buffer, thereby updating said page stored therein to include said one or more changes associated with said one or more write requests.

13. The method defined in claim 12 including the additional step of providing a NAND flash memory as said non-volatile memory.

14. The method defined in claim 12 including the additional step of providing a multi-level cell (MLC) NAND flash memory as said non-volatile memory.

15. The method defined in claim 12 including the additional step of providing as said volatile memory one of (i) a dynamic random access memory (DRAM) and (ii) a static random access memory (SRAM).

16. The method defined in claim 12 including the additional step of providing a static random access memory (SRAM) as said first buffer.