Memory access circuit and memory access system
First Claim
1. A memory access circuit connected to a memory comprising a parallel interface and a system circuit configured to issue a memory access command to command access to the memory, the memory access circuit comprising:
- a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal;
a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal;
a first delay locked loop configured to correct a clock skew between the reference clock signal and a system clock signal generated by the system circuit, and to generate a source signal of the system clock signal;
a second delay locked loop configured to correct a clock skew between the reference clock signal and a phy-clock signal used in the memory access circuit, and to generate a source signal of the phy-clock signal;
a first phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a first detection signal corresponding to the phase difference;
a second phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a second detection signal corresponding to the phase difference; and
a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, whereinthe first delay locked loop determines a correction direction and a correction amount based on the first detection signal and the delay correction signal, respectively; and
the second delay locked loop determines a correction direction and a correction amount based on the second detection signal and the delay correction signal, respectively.
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Accused Products
Abstract
According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.
15 Citations
20 Claims
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1. A memory access circuit connected to a memory comprising a parallel interface and a system circuit configured to issue a memory access command to command access to the memory, the memory access circuit comprising:
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a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal; a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal; a first delay locked loop configured to correct a clock skew between the reference clock signal and a system clock signal generated by the system circuit, and to generate a source signal of the system clock signal; a second delay locked loop configured to correct a clock skew between the reference clock signal and a phy-clock signal used in the memory access circuit, and to generate a source signal of the phy-clock signal; a first phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a first detection signal corresponding to the phase difference; a second phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a second detection signal corresponding to the phase difference; and a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein the first delay locked loop determines a correction direction and a correction amount based on the first detection signal and the delay correction signal, respectively; and the second delay locked loop determines a correction direction and a correction amount based on the second detection signal and the delay correction signal, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory access system comprising:
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a memory comprising a parallel interface; a system circuit configured to issue a memory access command to command an access to the memory; and a memory access circuit connected to the memory and the system circuit;
whereinthe memory access circuit comprises, a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal, a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal, a first delay locked loop configured to correct a clock skew between the reference clock signal and a system clock signal generated by the system circuit, and to generate a source signal of the system clock signal, a second delay locked loop configured to correct a clock skew between the reference clock signal and a phy-clock signal used in the memory access circuit, and to generate a source signal of the phy-clock signal, a first phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a first detection signal corresponding to the phase difference, a second phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a second detection signal corresponding to the phase difference; and a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein the first delay locked loop determines a correction direction and a correction amount based on the first detection signal and the delay correction signal, respectively; and the second delay locked loop determines a correction direction and a correction amount based on the second detection signal and the delay correction signal, respectively. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A memory access circuit connected to a memory comprising a parallel interface and a system circuit configured to issue a memory access command to command access to the memory and to generate a system clock signal;
- the memory access circuit comprising;
a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal from the system clock signal; a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal; a delay locked loop configured to correct a clock skew between the reference clock signal and a phy clock signal used in the memory access circuit and to generate a source signal of the phy-clock signal; a phase detector configured to detect a phase difference between the reference clock signal and the phy-clock signal, and to generate a detection signal corresponding to the phase difference; and a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein the delay locked loop determines a correction direction and a correction amount based on the detection signal and the delay correction signal, respectively. - View Dependent Claims (18, 19, 20)
- the memory access circuit comprising;
Specification