Architecture for optimizing execution of storage access commands

• US 8,825,940 B1
• Filed: 12/02/2008
• Issued: 09/02/2014
• Est. Priority Date: 12/02/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: SiliconSystems, Inc. (Western Digital Corporation)
• Inventors: Diggs, Mark S.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): GOLDSCHMIDT, CRAIG S
• Application Number:
  US12/326,780
• Time in Patent Office: 2,100 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Systems and methods for an architecture for optimizing execution of storage access commands is disclosed. The architecture enables a storage subsystem to execute storage access commands while satisfying one or more optimization criteria. The architecture thereby provides predictable execution times of storage access commands performed on a storage subsystem. In order to optimize execution of storage access commands, in one embodiment the host system sends a calibration request specifying a storage access command and an optimization criterion. In response to the calibration request, the storage subsystem determines the execution speeds of the storage access command within the non-volatile memory storage array and selects at least one region within the non-volatile memory storage array having the execution speed that satisfies the optimization criterion. Subsequently, when the host system desires that a storage access command be executed in satisfaction of the optimization criterion, the storage subsystem executes the command within the selected region.

Claims

1. In a storage subsystem that processes storage access commands received from a host system, a method of optimizing execution of storage access commands, the method comprising:

receiving a calibration request from the host system, the request specifying a first write command and an optimization criterion;

determining a speed of execution of the first write command, the determining comprising;

using power provided by a primary power source, executing the first write command, and

recording the execution speed of the first write command for each of a plurality of regions of a non-volatile memory storage device;

selecting a region from the plurality of regions having a recorded execution speed that satisfies the optimization criterion; and

when there is a failure of the primary power source, executing, using power provided by a reserve power source, a second write command directed to the selected region, wherein overhead operations that are directed to the selected region are disabled until the second write command has finished executing, the overhead operations comprising block erase, wear leveling, and bad block management operations.

2. The method of claim 1, wherein the selecting comprises selecting a region having the fastest recorded execution speed.

3. The method of claim 1, further comprising executing one or more block erase operations directed to the selected region prior to executing the second write command so that no block erase operations are performed that are directed to the selected region during the execution of the second write command.

4. The method of claim 1, further comprising executing one or more wear leveling operations directed to the selected region prior to executing the second write command so that no wear leveling operations are performed that are directed to the selected region during the execution of the second write command.

5. The method of claim 1, further comprising disabling execution of one or more wear leveling operations directed to the selected region so that no wear leveling operations are performed that are directed to the selected region during the execution of the second write command, wherein the one or more wear leveling operations comprise distributing write operations across memory locations of the selected region.

6. The method of claim 1, further comprising executing one or more bad block management operations directed to the selected region prior to executing the second write command so that no bad block management operations are performed that are directed to the selected region during the execution of the second write command.

7. The method of claim 1, further comprising:

executing one or more block erase operations directed to the selected region prior to executing the second write command; and

executing one or more wear leveling operations directed to the selected region prior to executing the second write command so that no block erase and wear leveling operations are performed that are directed to the selected region during the execution of the second write command.

8. The method of claim 1, further comprising:

executing one or more block erase operations directed to the selected region prior to executing the second write command; and

disabling execution of one or more wear leveling operations directed to the selected region so that no block erase and wear leveling operations are performed that are directed to the selected region during the execution of the second write command, wherein the one or more wear leveling operations comprise distributing write operations across memory locations of the selected region.

9. The method of claim 1, wherein the region comprises a contiguous region.

10. A method of optimizing execution of storage access commands communicated by a host system to a storage subsystem having a non-volatile memory storage device comprising a plurality of regions, the method comprising:

communicating a calibration request to the storage subsystem, the request specifying a first write command and an optimization criterion and causing the storage subsystem to perform calibration of the non-volatile memory storage device using power provided by a primary power source;

in response to the calibration request, receiving an identification of a region of the plurality of regions within the non-volatile memory storage device, the region having a speed of execution of the first write command that satisfies the optimization criterion;

communicating a second write command to the storage subsystem using power provided by a reserve power source, the command comprising the identification of the region embedded as a pattern within the second write command; and

causing execution of the second write command directed to the region in response to detecting a condition requiring the second write command to be executed in a time-critical manner, wherein the execution is performed using power provided by the reserve power source and wherein overhead operations that are directed to the region are disabled until the second write command has finished executing, the overhead operations comprising block erase, wear leveling, and bad block management operations.

11. The method of claim 10, wherein the identification comprises a memory address within the region.

12. The method of claim 10, further comprising mapping the region to a logical drive on the host system, wherein the second write command is directed to the mapped logical drive.

13. The method of claim 10, further comprising mapping the region to a file on the host system, wherein the second write command is directed to the mapped file.

14. The method of claim 10, further comprising:

in response to communicating the calibration request, receiving an execution time of the first write command; and

performing one or more time-critical tasks based at least in part on the execution time, wherein the one or more time-critical tasks comprise backing up data, caching data, and programming data.

15. The method of claim 10, wherein communicating the calibration request comprises:

causing execution of the first write command directed to the plurality of regions of the non-volatile memory storage device;

receiving execution speed of the first write command for each of the plurality of regions; and

selecting a region from the plurality of regions having an execution speed that satisfies the optimization criterion.

16. A storage subsystem comprising:

a non-volatile memory storage device; and

a controller that accesses the non-volatile memory storage device in response to storage access commands received from a host system, the controller configured to;

receive a calibration request from the host system, the request specifying a first write command and an optimization criterion;

in response to receiving the calibration request, and using power from a primary power source;

execute the first write command directed to a plurality of regions of the non-volatile memory storage device, record an execution speed of the first write command for each of the plurality of regions, and

select a region from the plurality of regions having the recorded execution speed that satisfies the optimization criterion;

receive a second write command; and

execute, using power from a reserve power source, the second write command directed to the selected region in response to detecting a condition requiring the second write command to be executed in a time-critical manner, wherein overhead operations that are directed to the selected region are disabled until the second write command has finished executing, the overhead operations comprising block erase, wear leveling, and bad block management operations.

17. The storage subsystem of claim 16, wherein the non-volatile storage device comprises a solid-state storage device.

18. The storage subsystem of claim 16, wherein the controller selects the region having the fastest recorded execution speed.

19. The storage subsystem of claim 16, wherein the controller is further configured to execute one or more block erase operations directed to the selected region prior to executing the second write command so that no block erase operations are performed that are directed to the selected region during the execution of the second write command.

20. The storage subsystem of claim 16, wherein the controller is further configured to execute one or more wear leveling operations directed to the selected region prior to executing the second write command so that no wear leveling operations are performed that are directed to the selected region during the execution of the second write command.

21. The storage subsystem of claim 16, wherein the controller is further configured to disable execution of one or more wear leveling operations directed to the selected region so that no wear leveling operations are performed that are directed to the selected region during the execution of the second write command, wherein the one or more wear leveling operations comprise distributing write operations across memory locations of the selected region.

22. The storage subsystem of claim 16, wherein the controller is further configured to execute one or more bad block management operations directed to the selected region prior to the execution of the second write command so that no bad block management operations are performed that are directed to the selected region during the execution of the second write command.

23. The storage subsystem of claim 16, wherein the controller is further configured to:

execute one or more block erase operations directed to the selected region prior to the execution of the second write command; and

execute one or more wear leveling operations that are directed to the selected region prior to the execution of the second write command so that no block erase and wear leveling operations are performed in the selected region during the execution of the second write command.

24. The storage subsystem of claim 16, wherein the controller is further configured to:

execute one or more block erase operations directed to the selected region prior to the execution of the second write command; and

disable execution of one or more wear leveling operations directed to the selected region so that no block erase and wear leveling operations are performed that are directed to the selected region during the execution of the second write command, wherein the one or more wear leveling operations comprise distributing write operations across memory locations of the selected region.