Power saving method for coded transmission

• US 8,826,093 B2
• Filed: 01/18/2006
• Issued: 09/02/2014
• Est. Priority Date: 01/19/2005
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Walker, Gordon Kent, Ganapathy, Chinnappa K., Radhakrishnan, Dhinakar, Ling, Fuyun, Vijayan, Rajiv
• Primary Examiner(s): Vu, Michael T
• Application Number:
  US11/335,013
• Publication Number:
  US 20060195752A1
• Time in Patent Office: 3,149 Days
• Field of Search: 714/704, 714/758, 714/781, 714/714, 714/746, 714748-749, 714751-752, 714/799, 714/801, 709/231, 709/236, 370/395.1, 370/473, 370/394, 370428-429, 370277-278, 370/282, 370290-292, 455/574, 455/343, 455/517, 455/522, 375/259
• US Class Current: 714/748
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control

Abstract

Conserving power for coded transmissions comprises ceasing to process parity packets once associated data packets are deemed correct or corrected. Once data packets are deemed correct or corrected, the receiving unit can shut off during the transmission of parity packets.

Claims

1. A method of wireless communications, comprising:

using an antenna of an apparatus for receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

buffering the parity packets in a buffer of the apparatus;

when the parity packets are received after the data packets;

detecting, at the apparatus, whether the data packets are incorrect using the CRC segments;

after the detecting, reducing power consumption by omitting to decode and deleting the parity packets from the buffer of the apparatus if all data packets are valid; and

decoding parity packets for error correction only if a data packet is determined to be incorrect; and

when the parity packets are received prior to the data packets;

decoding the parity packets; and

decoding the data packets without employing a CRC protocol if none of the of the data packets are corrupt.

5. The method of claim 1, further comprising decoding the parity packet before decoding the one or more data packets and determining whether the one or more data packets are corrupt to reduce latency when the parity packets are received prior to the data packets.

6. The method of claim 1, further comprising decoding a data packet and employing information contained in a CRC segment of the data packet to validate the data packet when the parity packets are received after the data packets.

7. The method of claim 6, further comprising decoding the parity packet if at least one of the one or more data packets is invalid when the parity packets are received after the data packets.

8. The method of claim 6, further comprising reducing power consumption by omitting to decode the parity packet if all of the one or more data packets are valid as determined by respective CRCs when the parity packets are received after the data packets.

2. The method of claim, further comprising receiving the parity packets after receiving the data packets.

3. The method of claim 2, further comprising decoding a data packet and employing information contained in a CRC segment of the data packet to validate the data packet.

4. The method of claim 3, further comprising decoding the parity packet if at least one of the one or more data packets is invalid.

9. An apparatus for facilitating conserving power during receipt of coded transmissions in a wireless communication environment, comprising:

a receiver configured to receive data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, and to buffer the parity packets in a buffer, wherein a parity packet is associated with one or more data packets; and

a processor configured to;

when the parity packets are received after the data packets;

detect errors based on the CRC segments;

determine whether to decode the parity packets based at least in part on the detected errors related to data packet corruption; and

reduce power consumption after the detection by omitting to decode and deleting the parity packets from the buffer if all data packets are valid; and

when the parity packets are received prior to the data packets;

decode the parity packets; and

decode the data packets without employing a CRC protocol if none of the one or more data packets are corrupt.

10. The apparatus of claim 9, wherein the receiver is operable to receive the parity packet after the one or more data packets associated therewith.

11. The apparatus of claim 10, wherein the processor is operable to evaluate data packet validity for each data packet to determine whether the data packet is corrupt.

12. The apparatus of claim 10, wherein the processor is operable to decode a data packet and employ information contained in a CRC segment of the data packet to validate the data packet.

13. The apparatus of claim 12, wherein the processor is operable to decode the parity packet if at least one of the one or more data packets is corrupt.

14. The apparatus of claim 9, wherein the processor is operable to decode the parity packet before decoding the one or more data packets and to determine whether the one or more data packets are corrupt to reduce latency when the parity packets are received prior to the data packets.

15. The apparatus of claim 9, wherein the processor is operable to decode a data packet employing information contained in a CRC segment of the data packet to validate the data packet when the parity packets are received after the data packets.

16. The apparatus of claim 15, wherein the processor is operable to decode the parity packet if at least one of the one or more data packets is invalid.

17. The apparatus of claim 15, wherein the processor is operable to reduce power consumption by omitting to decode the parity packet if all of the one or more data packets are valid as determined by respective CRCs when the parity packets are received after the data packets.

18. A receiving unit, comprising:

means for receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

means for buffering the parity packets in a buffer;

means for detecting whether the data packets are incorrect using the CRC segments when the parity packets are received after the data packets;

means for, after the detecting, reducing power consumption by omitting to decode and deleting the parity packets from the buffer if all data packets are valid when the parity packets are received after the data packets;

means for decoding the buffered parity packets for error correction only if a data packet is determined to be incorrect when the parity packets are received after the data packets;

means for decoding the parity packets when the parity packets are received prior to the data packets; and

means for decoding the data packets without employing a CRC protocol if none of the of the data packets are corrupt when the parity packets are received prior to the data packets.

19. The receiving unit of claim 18, the means for receiving is operable to receive a set of data packets followed by an associated parity packet.

20. The receiving unit of claim 19, the means for detecting comprises means for performing the CRC protocol when the parity packets are received after the data packets.

21. The receiving unit of claim 18, the means for receiving is operable to receive the parity packet prior to receiving one or more data packets associated with the parity packet.

22. A non-transitory computer-readable medium embodying a method of wireless communications, comprising instructions for:

receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

buffering the parity packets in a buffer of an apparatus;

when the parity packets are received after the data packets;

detecting, at the apparatus, whether the data packets are incorrect using the CRC segments;

after the detecting, reducing power consumption by omitting to decode and deleting the parity packets from the buffer of the apparatus if all data packets are valid; and

decoding parity packets for error correction only if a data packet is determined to be incorrect; and

when the parity packets are received prior to the data packets;

decoding the parity packets; and

decoding the data packets without employing a CRC protocol if none of the of the data packets are corrupt.

23. The non-transitory computer-readable medium of claim 22, further comprising instructions for receiving a set of data packets prior to receiving an associated parity packet.

24. The non-transitory computer-readable medium of claim 23, further comprising instructions for performing the CRC protocol when the parity packets are received after the data packets.

25. The non-transitory computer-readable medium of claim 22, further comprising instructions for receiving the parity packet prior to receiving one or more data packets associated with the parity packet.

26. A method of wireless communications, comprising:

using an antenna of an apparatus for receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

buffering the parity packets in a buffer of the apparatus;

when the parity packets are received after the data packets;

detecting, at the apparatus, whether the data packets are incorrect using the CRC segments;

reducing power consumption, at the apparatus, by omitting to decode and deleting the parity packets from the buffer if all data packets are valid; and

decoding, at the apparatus, parity packets for error correction only if a data packet is determined to be incorrect; and

when the parity packets are received after the data packets;

decoding, at the apparatus the parity packet before decoding the one or more data packets; and

determining, at the apparatus, whether the one or more data packets are corrupt to reduce latency.

27. An apparatus for facilitating conserving power during receipt of coded transmissions in a wireless communication environment, comprising:

a receiver configured to receive data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, and to buffer the parity packets in a buffer, wherein a parity packet is associated with one or more data packets;

a processor configured to;

when the parity packets are received after the data packets;

detect errors based on the CRC segments

determine whether to decode the parity packets based at least in part or the detected errors related to data packet corruption; and

reduce power consumption by omitting to decode and deleting the parity packets from the buffer if all data packets are valid; and

when the parity packets are received after the data packets;

decode the parity packet before decoding the one or more data packets; and

determine whether the one or more data packets are corrupt to reduce latency.

28. A receiving unit, comprising:

means for receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

means for buffering the parity packets in a buffer;

means for detecting whether the data packets are incorrect using the CRC segments when the parity packets are received after the data packets;

means for reducing power consumption by omitting to decode and deleting the parity packets from the buffer if all data packets are valid when the parity packets are received after the data packets;

means for decoding the buffered parity packets for error correction only if a data packet is determined to be incorrect when the parity packets are received after the data packets;

means for decoding a parity packet before decoding one or more data packets when the parity packets are received prior to the data packets; and

means for determining whether the one or more data packets are corrupt to reduce latency when the parity packets are received prior to the data packets.

29. A non-transitory computer-readable medium embodying a method of wireless communications, comprising instructions for:

receiving data packets, cyclic redundancy check (CRC) segments and parity packets in a superframe, wherein a parity packet is associated with one or more data packets;

buffering the parity packets in a buffer;

when the parity packets are received after the data packets;

detecting whether the data packets are incorrect using the CRC segments;

reducing power consumption by omitting to decode and deleting the parity packets from the buffer if all data packets are valid; and

decoding parity packets for error correction only if a data packet is determined to be incorrect; and

when the parity packets are received after the data packets;

decoding the parity packet before decoding the one or more data packets; and

determining whether the one or more data packets are corrupt to reduce latency.