Dynamically configurable MLC state assignment

• US 8,830,752 B2
• Filed: 06/17/2013
• Issued: 09/09/2014
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fernandes, Brandon Lee
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/919,693
• Publication Number:
  US 20130279252A1
• Time in Patent Office: 449 Days
• Field of Search: 365/185.12
• US Class Current: 365/185.12
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition.

Claims

1. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request; and

wherein the control circuitry is configured to determine whether data read from the lower page should be inverted before outputting that data, regardless of a value of data of the upper page and regardless of a value of the data read from the lower page.

2. The memory device of claim 1, wherein the control circuitry is further configured to determine whether an inversion flag, corresponding to the data read from the lower page, is set to determine whether data read from the lower page should be inverted before outputting that data.

3. The memory device of claim 2, wherein the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag is set and to output the data read from the lower page without inverting that data if the inversion flag is not set.

4. The memory device of claim 2, wherein the control circuitry is further configured to determine whether the inversion flag is set in parallel with reading the data from the lower page.

5. The memory device of claim 1, wherein the control circuitry is further configured to output the data read from the upper page without determining whether that data should be inverted before output.

6. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request;

wherein the control circuitry is configured to read an inversion flag corresponding to data read from the lower page concurrently with reading the lower page; and

wherein the control circuitry is configured to determine, in response to a value of the inversion flag, whether data read from the lower page should be inverted before outputting that data.

7. The memory device of claim 6, wherein the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag has a first value, and to output the data read from the lower page without inverting that data if the inversion flag has a second value different from the first value.

8. The memory device of claim 6, wherein the control circuitry is further configured to output the data read from the upper page without determining whether that data should be inverted before output.

9. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request;

wherein, if the data is to be read from the upper page, the control circuitry is configured to output the data read from the upper page; and

wherein, if the data is to be read from the lower page, the control circuitry is configured to determine whether the data read from the lower page should be inverted before outputting that data, regardless of a value of the data of the upper page and regardless of a value of the data read from the lower page.

10. The memory device of claim 9, wherein the control circuitry is further configured to determine a value of an inversion flag, corresponding to the data read from the lower page, to determine whether the data read from the lower page should be inverted before outputting that data.

11. The memory device of claim 10, wherein the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag has a particular value and to output the data read from the lower page without inverting that data if the inversion flag has a value other than the particular value.

12. The memory device of claim 10, wherein the control circuitry is further configured to determine the value of the inversion flag after reading the data from the lower page.

13. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request;

wherein, if the data is to be read from the lower page;

the control circuitry is configured to read an inversion flag corresponding to the data read from the lower page;

the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag has a particular value, wherein the data read from the lower page are inverted regardless of a value of data of the upper page and regardless of a value of the data read from the lower page; and

the control circuitry is configured to output the data read from the lower page without inverting that data if the inversion flag has a value other than the particular value; and

wherein, if the data is to be read from the upper page, the control circuitry is configured to output the data read from the upper page.