Receive beamformer for ultrasound

• US 8,834,369 B2
• Filed: 06/18/2009
• Issued: 09/16/2014
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Magee, David P
• Primary Examiner(s): EVOY, NICHOLAS LANE
• Application Number:
  US12/487,097
• Publication Number:
  US 20090326375A1
• Time in Patent Office: 1,916 Days
• Field of Search: None
• US Class Current: 600/437
• CPC Class Codes: G01S 15/8915 using a transducer array
• CPC Class Codes: G01S 7/52046 Techniques for image enhancement involving transmitter or receiver image enhancement by image data processing G06T5/00
• CPC Class Codes: G10K 11/346 using phase variation

Abstract

A method of ultrasound receive beamforming includes receiving a first plurality of sensing signals from target tissue, forming a first plurality of digital sensing signals, and data processing the digital sensing signals along a first plurality of data paths to form a first plurality of delayed and apodized digital sensing signals. Data path combining generates data combinations of the delayed and apodized digital sensing signals to include two or more of the delayed and apodized digital sensing signals that originate from different ones of the transducer elements. The data combinations are interpolation filtered using a plurality of interpolation filters to form a second plurality of delayed and apodized digital sensing signals, which are then summed to form an ultrasound receive beamformed signal. The interpolation filters can be interpolation filters in a single shared filter bank, with each interpolation filter providing a different fractional delay.

Claims

1. A digital signal processor (DSP) integrated circuit (IC) for ultrasound signal processing, comprising:

a substrate having a semiconductor surface;

integer delaying and apodizing circuitry configured to process a first plurality of digitized ultrasound sensing signals to form a first plurality of delayed and apodized digital ultrasound sensing signals,

data path combining circuitry configured to generate a plurality of data combinations of said first plurality of delayed and apodized digital sensing signals to include two or more of said first plurality of delayed and apodized digital sensing signals, each delayed and apodized digital ultrasound sensing signal having its own data path, that originate from a plurality of different transducers of a first plurality of transducer elements,

a shared interpolation filter bank having a plurality of interpolation filters, each coupled to an output of said data path combining circuitry, for interpolation filtering said plurality of data combinations to generate a second plurality of delayed and apodized digital sensing signals, said shared interpolation filter bank comprising a plurality of interpolation filters, wherein the number of interpolation filters is set by a desired timing resolution and the number of interpolation filters is less than a number of said first plurality of transducer elements, wherein said plurality of interpolation filters each provides a different delay; and

wherein said data path combining circuitry comprises a switching circuit that is operable to direct any of said first plurality of delayed and apodized digital sensing signals to any of said plurality of interpolation filters upon receiving a control signal, and

an adder having a plurality of inputs, each coupled to an output of each of the plurality of the interpolation filters.

2. The digital signal processor (DSP) integrated circuit (IC) of claim 1, wherein said different delays are defined by an integer value multiplied by Tres, wherein Tres is the timing resolution (Tres) for said ultrasound receive beamformed signal and said integer value corresponds to integer values from zero to ceil(Ts/Tres)−

1, where Ts is a sampling period for said digitizing of said digitizing signal.

3. The digital signal processor (DSP) integrated circuit (IC) of claim 1, wherein a plurality of pre-summing blocks are interposed between the switching block and the shared interpolation filter bank.