Strained gate electrodes in semiconductor devices
First Claim
1. A method of forming an integrated circuit, the method comprising:
- providing a substrate;
forming a gate dielectric layer over the substrate;
forming a gate electrode layer over the gate dielectric layer, the gate electrode layer being crystalline or polycrystalline;
amorphizing, after the forming the gate electrode layer, only an upper portion of the gate electrode layer, thereby creating an amorphized gate electrode layer, a lower portion of the gate electrode layer remaining crystalline or polycrystalline, the lower portion of the gate electrode having a first grain structure, the lower portion of the gate electrode layer being interposed between the upper portion of the gate electrode layer and the substrate;
recrystallizing the upper portion of the gate electrode layer such that the upper portion has a second grain structure after the recrystallizing, the second grain structure being a different grain structure than the first grain structure of the lower portion; and
after the amorphizing, patterning the gate electrode layer to form a gate electrode.
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Abstract
Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.
46 Citations
20 Claims
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1. A method of forming an integrated circuit, the method comprising:
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providing a substrate; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer, the gate electrode layer being crystalline or polycrystalline; amorphizing, after the forming the gate electrode layer, only an upper portion of the gate electrode layer, thereby creating an amorphized gate electrode layer, a lower portion of the gate electrode layer remaining crystalline or polycrystalline, the lower portion of the gate electrode having a first grain structure, the lower portion of the gate electrode layer being interposed between the upper portion of the gate electrode layer and the substrate; recrystallizing the upper portion of the gate electrode layer such that the upper portion has a second grain structure after the recrystallizing, the second grain structure being a different grain structure than the first grain structure of the lower portion; and after the amorphizing, patterning the gate electrode layer to form a gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming an integrated circuit, the method comprising:
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providing a substrate; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer, the gate electrode layer being crystalline or polycrystalline; amorphizing, after the forming the gate electrode layer, at least a portion of the gate electrode layer, thereby creating an amorphized gate electrode layer; stabilizing an amorphous phase of an upper surface of the gate electrode layer, the stabilizing being performed at least in part by forming a cap layer over the gate electrode layer; crystallizing at least a portion of the amorphized gate electrode layer, the crystallizing being performed while the cap layer is over the gate electrode layer; and implanting ions to form source/drain regions, the implanting being a separate process from the amorphizing. - View Dependent Claims (10, 11, 12)
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13. A method of forming an integrated circuit, the method comprising:
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providing a substrate; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer; forming a mask layer over at least a portion of the gate electrode layer; amorphizing, after the forming the mask layer, at least a portion of the gate electrode layer, thereby creating an amorphized gate electrode layer, the mask layer reducing the amorphizing of the gate electrode layer underlying the mask layer; forming a cap layer over the gate electrode layer; crystallizing at least a portion of the amorphized gate electrode layer; and implanting ions to form source/drain regions, the implanting being a separate process from the amorphizing.
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14. A method of forming an integrated circuit, the method comprising:
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providing a substrate, the substrate having a first section and a second section; forming a dielectric layer over the substrate in the first section and the second section; forming a first layer over the dielectric layer in the first section and the second section; forming a mask layer over the first layer in the first section; amorphizing at least a portion of the first layer in the second section, the amorphizing converting the portion of the first layer from a crystalline or polycrystalline region to an amorphous region; removing the mask layer; forming a nitrogen-containing cap layer over the first layer in the first section and the second section, the nitrogen-containing cap layer stabilizing a solid phase structure of the first layer; at least partially crystallizing the amorphized region of the first layer, the at least partially crystallizing the amorphized region being performed while the nitrogen-containing cap layer is over the first layer; and forming, after the at least partially crystallizing, lightly doped source/drain regions. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification