System for injecting protocol specific errors during the certification of components in a storage area network

• US 8,843,786 B2
• Filed: 06/05/2013
• Issued: 09/23/2014
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Jibbe, Mahmoud K., Palanisamy, Prakash
• Primary Examiner(s): Manoskey, Joseph D
• Application Number:
  US13/910,319
• Publication Number:
  US 20140013152A1
• Time in Patent Office: 475 Days
• Field of Search: 714/4.1, 714/4.5, 714/25, 714/35, 714/37, 714/41, 714/43, 714/47.1, 714/56
• US Class Current: 714/41
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Claims

1. An apparatus comprising:

an initiator circuit configured to (i) communicate with a network, (ii) generate a plurality of testing sequences from a plurality of values stored in a file, (iii) create one or more errors in said testing sequences by altering said file and (iv) transmit said file including said testing sequences on said network; and

a target circuit configured to (i) receive said file including said testing sequences from said network, (ii) generate a plurality of responses to said testing sequences and (iii) transmit said responses on said network to said initiator circuit, wherein said initiator circuit is further configured to verify that said target properly responded to said errors in said testing sequences.

2. The apparatus according to claim 1, wherein said target circuit comprises a RAID controller.

3. The apparatus according to claim 1, wherein said initiator circuit comprises a testing section configured to (i) generate said testing sequences in a first state and (ii) generate error-free sequences from said values in a second state.

4. The apparatus according to claim 1, wherein said errors introduced in said testing sequences comprise protocol specific error sequences configured to simulate protocol specific errors.

5. The apparatus according to claim 4, wherein said protocol specific errors simulate errors in a network environment.

6. The apparatus according to claim 5, wherein said network environment comprises a fibre channel network.

7. The apparatus according to claim 4, wherein said protocol specific errors comprise simulated errors in an Internet Small Computer System Interface (iSCSI) protocol.

8. The apparatus according to claim 4, wherein said protocol specific errors simulate errors that are remotely generated.

9. The apparatus according to claim 1, wherein said initiator circuit includes a software module configured to generate said errors in said file prior to generation of said testing sequences.

10. The apparatus according to claim 9, wherein said software module is updatable.

11. The apparatus according to claim 1, wherein said file is generated in a virtual directory structure compatible with a specific operating system.

12. The apparatus according to claim 11, wherein said specific operating system comprises a Linux operating system.

13. An apparatus comprising:

means for communicating with a network;

means for generating a plurality of testing sequences from a plurality of values stored in a file;

means for creating one or more errors in said testing sequences by altering said file;

means for transmitting said file including said testing sequences on said network;

means for receiving said file including testing sequences from said network;

means for generating a plurality of responses to said testing sequences;

means for transmitting said responses on said network to said means for communicating with said network; and

means for verifying that said means for receiving said testing sequences properly responded to said errors in said testing sequences.

14. A method for testing via a network comprising the steps of:

(A) communicating with said network with an initiator circuit;

(B) generating a plurality of testing sequences from a plurality of values stored in a file within said initiator circuit;

(C) creating one or more errors in said testing sequences by altering said file;

(D) transmitting said file including said testing sequences on said network;

(E) receiving said file including testing sequences from said network of a target circuit;

(F) generating a plurality of responses to said testing sequences;

(G) transmitting said responses on said network to said initiator circuit; and

(H) verifying that said method properly responded to said errors in said testing sequences by said initiator circuit.

15. The method according to claim 14, wherein said errors introduced in said testing sequences simulate protocol specific errors.

16. The method according to claim 14, wherein said errors are included in an initial generation of said testing sequences.

17. The method according to claim 14, further comprising the step of:

executing a software module in said initiator circuit to generate said errors in said file prior to generation of said testing sequences.

18. The method according to claim 14, wherein said testing sequences are generated in a first state, the method further comprising the step of:

generating error-free sequences from said values with said initiator circuit in a second state.

19. The method according to claim 18, further comprising the steps of:

generating a plurality of response sequences in response to said error-free sequences with said target circuit; and

creating one or more response errors in said response sequences.

20. The method according to claim 19, further comprising the steps of:

transmitting said response sequences to said initiator circuit; and

verifying if said initiator circuit properly handles said response errors in said response sequences.