Semiconductor device

• US 8,847,276 B2
• Filed: 06/29/2011
• Issued: 09/30/2014
• Est. Priority Date: 07/01/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tanabe, Hiromitsu, Kouno, Kenji, Tsuzuki, Yukio
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US13/805,740
• Publication Number:
  US 20130087829A1
• Time in Patent Office: 1,189 Days
• Field of Search: 257/140, 257/288, 257/139, 257/197, 257/329, 257/330, 257/655, 257/656, 257/332, 257/335, 257/348
• US Class Current: 257/140
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 27/0722 in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/861 Diodes

Abstract

In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.

Claims

1. A semiconductor device including a cell region and a peripheral region, the cell region having a freewheeling diode and a vertical insulated gate bipolar transistor surrounded by the freewheeling diode, the peripheral region having a peripheral dielectric-strength structure that surrounds the cell region, the semiconductor device comprising:

a first conductivity type drift layer;

a second conductivity type collector region located on a back side of the drift layer in the cell region and peripheral region;

a first conductivity type cathode region located on the back side of the drift layer in the cell region at a position where the collector region is not located;

a second conductivity type base region located in a superficial part of a front side of the drift layer in the cell region at positions where the insulated gate bipolar transistor and the freewheeling diode are located;

a first conductivity type emitter region located in a superficial part of the base region;

a gate insulating film located on a surface of the base region between the emitter region and the drift layer;

a gate electrode located on the gate insulating film;

a second conductivity type deep well layer located in the superficial part of the front side of the drift layer in the cell region at the position where the freewheeling diode is located, the deep well layer located to surround a periphery of the base region and connected to the base region, the deep well layer being deeper than the base region and having an impurity concentration greater than that of the base region;

an upper electrode electrically connected to the emitter region, the base region, and the deep well layer; and

a lower electrode electrically connected to the collector region and the cathode region, wherein

W3≧

((k2·

(Dτ

)^1/2)²−

L1²)^(½

),

W2≧

L1/K^1/2, where K≧

2.5,

W2−

W1≧

10 μ

m,

W1 denotes a distance from a boundary between the cathode region and the collector region to a first position, where a peripheral-region-side end of the deep well layer is projected, on the back side of the drift layer,

W2 denotes a distance from a boundary between the insulated gate bipolar transistor and the freewheeling diode in the base region to the peripheral-region-side end of the deep well layer,

W3 denotes a distance from the boundary between the cathode region and the collector region to a second position, where a boundary between the base region and the deep well layer is projected, on the back side of the drift layer,

L1 denotes a thickness of the drift layer,

D denotes a carrier diffusion coefficient in the drift layer,

τ

denotes a carrier lifetime,

k1 denotes a first parameter that depends on structures of the insulated gate bipolar transistor and the freewheeling diode,

k2 denotes a second parameter that depends on a structure of the deep well layer, and

K denotes a value calculated by multiplying the first parameter k1 by a ratio of a snapback voltage to a built-in potential between the deep well layer and the drift layer.

2. The semiconductor device according to claim 1, wherein

W3=((k2·

(Dτ

)^1/2)²−

L1²)^(½

),

W2=L1/K^1/2, and

W2−

W1=10 μ

m.

3. The semiconductor device according to claim 1, wherein

the gate electrode is configured as a gate structure having a longitudinal direction,

the distance W1, the distance W2, and the distance W3 satisfy the following relationship at an end of the gate structure in the longitudinal direction,

W3≧

((k2·

(Dτ

)^1/2)²−

L1²)^(1/2),

W2≧

L1/K^1/2, where K≧

2.5, and

W2−

W1≧

10 μ

m.

4. The semiconductor device according to claim 3, wherein

the gate structure comprises a plurality of gate structures,

the emitter region is not formed in at least one region between the plurality of gate structures to define a first region and a second region,

the emitter region is formed in the first region so that the first region acts as the insulated gate bipolar transistor,

the emitter region is not formed in the second region so that the second region acts as the freewheeling diode,

a portion located to surround the insulated gate bipolar transistor is defined as a third region acting as the freewheeling diode, and

each of the first region and the second region has a longitudinal direction parallel to the longitudinal direction of the gate structure.

5. The semiconductor device according to claim 4, wherein

a width of the second region is 20 μ

m or more.

6. The semiconductor device according to claim 4, wherein

the cathode region has a longitudinal direction parallel to the longitudinal direction of the first region and extends beyond an end of the first region in the longitudinal direction, and

the cathode region is divided in the longitudinal direction.

7. The semiconductor device according to claim 4,

wherein the first region is divided in the longitudinal direction.

8. The semiconductor device according to claim 7, wherein

a region between the divided first regions is filled with the base region and acts as the freewheeling diode.

9. The semiconductor device according to claim 7, wherein the

cathode region has a longitudinal direction parallel to the longitudinal direction of the first region, and

the first region extends beyond an end of the cathode region in the longitudinal direction.

10. The semiconductor device according to claim 7, wherein

a distance between the divided first regions is two or more times greater than the distance W2.

11. The semiconductor device according to claim 7, wherein

the divided first region is further divided in the longitudinal direction,

a region between the further divided first regions has no emitter region and acts as the freewheeling diode, and

the cathode region is wider at a position corresponding to the region between the further divided first regions than at a position corresponding to the further divided first region.

12. The semiconductor device according to claim 4, wherein

the first region comprises a plurality of first regions that are arranged, and

opposing sides of adjacent first regions are partially recessed to form a recess region that acts as the freewheeling diode.

13. The semiconductor device according to claim 12, wherein

the cathode region has a longitudinal direction parallel to the longitudinal direction of the first region, and

the cathode region has the same width the recess region and is located to face the recess region.

14. The semiconductor device according to claim 4, wherein

the cathode region has a region which is located at a position corresponding to the second region, and

the cathode region has a region which is located at a position corresponding to the first region and narrower than the region located at the position corresponding to the second region.

15. The semiconductor device according to claim 1, wherein

a mixed region is located on the back side of the drift layer on an outer edge of the cell region, and

the mixed region has both the collector region and the cathode region.

16. The semiconductor device according to claim 1, further comprising:

a first conductivity type field stop layer located on the back side of the drift layer in the cell region and the peripheral region, wherein

an impurity concentration of the field stop layer is greater than that of the drift layer, and

the collector region and the cathode region are located in a superficial part of the field stop layer.

17. The semiconductor device according to claim 1, further comprising:

a plurality of trenches penetrating the base region, wherein

the plurality of trenches have a longitudinal direction and are arranged at a predetermined interval, and

the gate insulating film and the gate electrode are located in each trench to form a trench gate structure.

18. The semiconductor device according to claim 4, wherein

the second region and the third region are in contact with each other.