System, structure, and method of manufacturing a semiconductor substrate stack

• US 8,853,830 B2
• Filed: 07/23/2008
• Issued: 10/07/2014
• Est. Priority Date: 05/14/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Wu, Weng-Jin, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US12/178,021
• Publication Number:
  US 20090283871A1
• Time in Patent Office: 2,267 Days
• Field of Search: 257/621, 438/667
• US Class Current: 257/621
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Claims

1. An integrated circuit comprising:

a substrate having an active region formed in a top surface of the substrate;

a plurality of vias, each extending through the substrate, each having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned to the top surface of the substrate;

wherein each first termination of the plurality of vias terminate on a common plane at the bottom surface and are electrically insulated from one another;

a first conductive contact electrically connected to the second termination of at least one of the vias and electrically connected to a conductive interconnect layer;

a first bonding joint connected to the second termination of the via and extending above a topmost insulator of the substrate, wherein there is no semiconductor substrate between the top surface of the substrate and the first bonding joint; and

a second conductive contact electrically connected to the conductive interconnect layer and the active region.

2. The integrated circuit of claim 1 further comprising liner material substantially surrounding the respective vias and wherein the liner material does not surround the first conductive contact.

3. The integrated circuit of claim 2, wherein the liner material comprises a dielectric material.

4. The integrated circuit of claim 1, wherein the top surface of the substrate is a top surface of a semiconductor material.

5. The integrated circuit of claim 1 further comprising a second substrate wherein the second substrate has a second bonding joint connected to the substrate.

6. The integrated circuit of claim 5, wherein the first and second bonding joints are physically contacting.

7. The integrated circuit of claim 5 further comprising:

a contacting area_cc of the first conductive contact; and

a contacting area_via of at least one of the vias, wherein contacting area_cc is less than contacting area_via.

8. The integrated circuit of claim 5, further comprising a plurality of first conductive contacts contacting a single via.

9. The integrated circuit of claim 5, wherein a material of the first conductive contact is selected from the group consisting of Cu, W, alloy, or other conducting material.

10. The integrated circuit of claim 1, wherein there is no bulk layer of semiconductive material between the top surface of the substrate and the first bonding joint.

11. A semiconductor substrate structure, the structure comprising:

a backside;

a front-face;

a bulk layer;

an interconnect layer, wherein the interconnect layer includes a plurality of conductive layers sandwiched between inter-metal dielectric layers, the plurality of conductive layers being parallel to the front face;

a contact layer, wherein the contact layer is between the bulk layer and the interconnect layer;

a first through substrate via (TSV) commencing between the bulk layer and the contact layer and terminating at the backside of the bulk layer, wherein the first TSV is electrically coupled to the interconnect layer, and wherein the first TSV is electrically coupled to the backside;

a bonding region on the front-face, wherein the interconnect layer is between the bonding region and the first TSV and wherein the bonding region extends beyond a topmost surface of a topmost insulator on the front face, wherein there is no semiconductor substrate between the front face and the bonding region; and

a second TSV commencing between the bulk layer and the contact layer and terminating at the backside of the bulk layer, wherein the second TSV is electrically isolated from the first TSV.

12. The structure of claim 11 further comprising:

a lining, on sidewalls of the first TSV.

13. The structure of claim 12, wherein the first TSV comprises a metal that is isolated from the bulk layer by the lining, and wherein the lining is limited to the bulk layer.

14. The structure of claim 11 further comprising:

a plurality of contacts, wherein the first TSV is electrically coupled to the interconnect layer at least through a first contact, and

a circuit, wherein the circuit is electrically coupled to the interconnect layer at least through a second contact, wherein the first contact and the second contact are formed in the contact layer.

15. The structure of claim 11 further comprising:

a second substrate with a second bonding region, wherein the bonding region of the semiconductor substrate structure is bonded to the second bonding region of the second substrate.

16. The structure of claim 11, wherein the bulk layer is silicon.

17. The semiconductor substrate structure of claim 11, wherein there is no bulk layer of semiconductive material between the front face and the bonding region.

18. A system of stacked semiconductor substrates, the system comprising:

a first substrate including;

a backside;

a front-face;

a bulk layer, wherein the bulk layer comprises a semiconductor material;

a contact layer, wherein the contact layer is between the bulk layer and an interconnect layer;

wherein the interconnect layer includes a plurality of inter-metal dielectric layers sandwiched between a plurality of conductive layers, the plurality of inter-metal dielectric layers and plurality of conductive layers being parallel to the front-face, and wherein the interconnect layer does not contain a semiconductor substrate;

a plurality of lined TSVs commencing between the contact layer and terminating at the backside, wherein each lined TSV is electrically coupled to the interconnect layer and wherein each lined TSV is electrically coupled to a bonding pad on the backside, and further wherein each lined TSV is electrically isolated from an adjacent TSV; and

a bonding joint, wherein the bonding joint is on the front-face and is electrically and physically connected to the interconnect layer and further wherein the bonding joint extends beyond a top surface of a topmost insulator layer on the front face; and

a second substrate bonded to the first substrate at the bonding joint.

19. The system of stacked semiconductor substrates of claim 18, wherein a lining is disposed into each lined TSV prior to any first substrate metal processes.

20. The system of stacked semiconductor substrates of claim 18, wherein a bonding metal at the bonding joint is selected from the group consisting of Cu, W, Au, Sn, Pb and an alloy thereof.

21. The system of stacked semiconductor substrates of claim 18, wherein the interconnect layer does not contain a bulk layer of semiconductive material.

22. A semiconductor device comprising:

a first substrate comprising;

a bulk semiconductor layer having a top surface and a bottom surface;

an active region formed in the top surface of the bulk semiconductor layer;

a first TSV extending through the bulk semiconductor layer;

a second TSV extending through the bulk semiconductor layer, wherein the first and second TSVs each have a first termination at the top surface of the bulk semiconductor layer and a second termination at the bottom surface of the bulk semiconductor layer, and wherein the first TSV is electrically isolated from the second TSV;

a first conductive contact electrically and physically connected to the first termination of the first TSV; and

a second conductive contact electrically and physically connected to the active region;

an interconnect layer comprising a plurality of inter-metal dielectric layers sandwiched between a plurality of conductive layers, wherein the first and second conductive contacts are electrically and physically connected to the interconnect layer, and wherein the interconnect layer does not contain a semiconductor substrate; and

a first bonding joint electrically and physically connected to the interconnect layer and electrically connected to the first TSV, the first bonding joint extending beyond a top surface of a topmost insulator layer of the interconnect layer.

23. The semiconductor device of claim 22 further comprising a second substrate wherein the second substrate has a second bonding joint, the second bonding joint electrically and physically connected to the first bonding joint.

24. The semiconductor device of claim 23, wherein the first bonding joint comprises a material selected from a group consisting essentially of W, Al, Cu, Sn, Pb, or a combination thereof.

25. The semiconductor device of claim 22, wherein the interconnect layer does not contain a bulk semiconductive layer.

26. The semiconductor device of claim 22 further comprising a liner material on the sidewalls of the first TSV and the second TSV.

27. The semiconductor device of claim 22, wherein the first conductive contact comprises a plurality of conductive contacts contacting the first TSV.

28. The semiconductor device of claim 22, wherein the first conductive contact has a first contacting area, and wherein the first TSV has a second contacting are, the first contacting area being less than the second contacting area.

29. The semiconductor device of claim 22, wherein the first and second conductive contacts comprise a material selected from a group consisting essentially of W, Al, Cu, doped polysilicon, or a combination thereof.

30. The semiconductor device of claim 22, wherein the conductive layers in interconnect layer comprise a material selected from a group consisting essentially of W, Al, Cu, or a combination thereof.