Random number generator circuit and cryptographic circuit

• US 8,856,199 B2
• Filed: 11/22/2011
• Issued: 10/07/2014
• Est. Priority Date: 05/22/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanamoto, Tetsufumi, Matsumoto, Mari, Fujita, Shinobu, Ikegami, Kazutaka
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US13/301,932
• Publication Number:
  US 20120089656A1
• Time in Patent Office: 1,050 Days
• Field of Search: 708250-256
• US Class Current: 708/255
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.

Claims

1. A random number generator circuit comprising:

a physical random number generating element generating and outputting physical random numbers;

a digitizing circuit digitizing the physical random numbers and outputting a random number sequence;

a testing circuit testing the random number sequence;

a first memory storing information about error-correcting-code; and

an error correcting code circuit including;

a first XOR gate including an input terminal to receive digital random numbers that are sent as input signals;

a shift register including a plurality of flip-flops connected in series, one in a first stage of the flip-flops receiving an output of the first XOR gate;

a plurality of pass transistors corresponding to the respective flip-flops, one terminal of each of the pass transistors being connected to an output terminal of each corresponding one of the flip-flops, a gate of each of the pass transistors receiving a signal in accordance with the information stored in the first memory;

a plurality of second XOR gates corresponding to the respective pass transistors except one of the pass transistors corresponding to one in a first stage of the flip-flops and connected in series, one in a first stage of the second XOR gates performing an exclusive-OR operation on signals that are sent from another terminal of corresponding one of the pass transistors and another terminal of the one of the pass transistors corresponding to the one in the first stage of the flip-flops, each of the second XOR gates except the one in the first stage of the second XOR gates performing an exclusive-OR operation on signals that are sent from another terminal of each corresponding one of the pass transistors and an output terminal of each one in a precedent stage of the second XOR gates;

a switch being switched on and off in accordance with the result of a test conducted by the testing circuit, and sending an output of one in the last stage of the second XOR gates to the other input terminal of the first XOR gate; and

a selector switch selecting and outputting one of an output of the flip-flop in the last stage of the shift register and the output of the one in the last stage of the second XOR gates, in accordance with the result of the test conducted by the testing circuit, the error correcting code circuit outputting the output of the one in the last stage of the second XOR gates as a corrected random number sequence from the selector switch when the result of the test conducted by the testing circuit indicates a rejection, and

the testing circuit testing the corrected random number sequence when the result of the test indicates the rejection.

2. The circuit according to claim 1, wherein

the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and receives the random number sequence as digital random numbers from the digitizing circuit and sends the corrected random number sequence to the testing circuit.

3. The circuit according to claim 2, wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of an error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

4. The circuit according to claim 1, further comprising

a third XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,

wherein

the testing circuit tests a random number sequence that is output from the third XOR gate.

5. The circuit according to claim 4, wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of an error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

6. The circuit according to claim 1, further comprising a second memory,

wherein the error correcting code circuit is included in the second memory.

7. A cryptographic circuit comprising:

the random number generator circuit according to claim 1;

a second memory storing personal information; and

a CPU,

wherein, when the cryptographic circuit is connected to a system for personal verification, the CPU causes the error correcting code circuit to output the corrected random number sequence, to change random number quality.

8. The circuit according to claim 7, wherein

the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and receives the random number sequence as digital random numbers from the digitizing circuit and sends the corrected random number sequence to the testing circuit.

9. The circuit according to claim 8, wherein

the information stored in the first memory includes about a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

10. The circuit according to claim 7, further comprising

a third XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,

wherein

the testing circuit tests a random number sequence that is output from the third XOR gate.

11. The circuit according to claim 7, further comprising a third memory,

wherein the error correcting code circuit is included in the third memory.

13. A cryptographic circuit comprising:

the random number generator circuit according to claim 8;

a second memory storing personal information; and

a CPU,

wherein, when the cryptographic circuit is connected to a system for personal verification, the CPU causes the error correcting code circuit to output a corrected random number sequence, to change random number quality.

14. The circuit according to claim 13, wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of an error-correcting-code generating matrix,

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

15. The circuit according to claim 13, wherein

the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and receives the random number sequence as digital random numbers from the digitizing circuit and sends the corrected random number sequence to the testing circuit.

16. The circuit according to claim 15, wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

17. The circuit according to claim 13, further comprising

a fourth XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,

wherein the testing circuit tests a random number sequence that is output from the fourth XOR gate.

18. The circuit according to claim 17, wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of an error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

12. A random number generator circuit comprising:

a physical random number generating element generating and outputting physical random numbers;

a digitizing circuit digitizing the physical random numbers and outputting a random number sequence;

a testing circuit testing the random number sequence;

a first memory storing information about error-correcting-code; and

an error correcting code circuit including;

a shift register including a plurality of flip-flops connected in series;

a first XOR gate provided on an input side of the flip-flop in the input stage of the shift register;

a plurality of second XOR gates provided between the respective adjacent flip-flops;

a third XOR gate provided on an output side of the flip-flop in the last stage of the shift register;

a plurality of pass transistors corresponding to the respective first through third XOR gates, one terminal of each of the pass transistors being connected to an input terminal of each corresponding one of the XOR gates, the other terminals of the pass transistors being connected together, a gate of each of the pass transistors receiving a signal in accordance with a coefficient of a generator polynomial of the error correcting code generating matrix the information stored in the first memory;

a first selector switch circuit selectively sending an input signal to the other terminal of each of the pass transistors or to the other input terminal of the first XOR gate, in accordance with the result of a test conducted by the testing circuit; and

a second selector switch circuit selectively sending one of a signal at the other terminal of each of the pass transistors and an output of the third XOR gate, in accordance with the result of the test conducted by the testing circuit.

19. The circuit according to claim 12, wherein

the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and receives the random number sequence as digital random numbers from the digitizing circuit and sends the corrected random number sequence to the testing circuit.

20. The circuit according to claim 19,

wherein the information stored in the first memory includes a coefficient of each order of a generator polynomial of an error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.

21. The circuit according to claim 12, further comprising

a fourth XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,

wherein

the testing circuit tests a random number sequence that is output from the fourth XOR gate.

22. The circuit according to claim 21,

wherein

the information stored in the first memory includes a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix, and

wherein each of the gates of the pass transistors receives corresponding one of the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, and the pass transistors are switched on and off based on the information stored in the first memory.