Structure and method for making crack stop for 3D integrated circuits

• US 8,859,390 B2
• Filed: 02/05/2010
• Issued: 10/14/2014
• Est. Priority Date: 02/05/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G, Zhu, Huilong, Griesemer, John A, Landers, William F, Melville, Ian D, Shaw, Thomas M
• Primary Examiner(s): Jung, Michael
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US12/700,841
• Publication Number:
  US 20110193197A1
• Time in Patent Office: 1,712 Days
• Field of Search: 257/E23.194, 257/686, 257/777, 257/778, 257/E23.169, 361/714
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

Claims

1. A method of forming a 3D IC comprising the steps of:

providing a bonded structure comprising a first component bonded to a second component using a bonding layer, said first component having a first semiconductor substrate and a first layer with first metallization formed therein, said second component having a second semiconductor substrate that is substantially thinner than the first semiconductor substrate and a second layer with second metallization formed therein, and said bonding layer comprised of a first adhesion layer formed on the first layer and a second adhesion layer formed on the second layer, and said bonded structure having a periphery;

forming a crack stop in the first layer;

forming a passivation layer on said second semiconductor substrate;

forming one or more holes through said passivation layer, said second semiconductor substrate, said second layer, and said bonding layer; and

filling said one or more holes to form a circumferential wall, the circumferential wall contacting said crack stop and extending through said second semiconductor substrate, said second layer, and said bonding layer and adjacent to said periphery.

2. The method of claim 1 wherein said second component has an annular region peripheral to an active region and said forming one or more holes through said passivation layer, said second semiconductor substrate, said second layer, and said bonding layer comprises:

forming two or more rows of holes in said annular region, said holes extending generally perpendicular to said second semiconductor substrate and being generally parallel to each other, said holes and rows spaced and extended such that a straight line into said active region and through a) the periphery of said bonding layer or b) the periphery of said second semiconductor substrate necessarily intersects at least one said holes.

3. The method of claim 1 further comprising:

bonding said first component to said second component prior to said providing step by adhering the first adhesion layer to the second adhesion layer and thereby forming the bonding layer.

4. The method of claim 3 further comprising prior to said bonding step:

forming one or more holes through said second adhesion layer and said second layer; and

filling said one or more holes to form said circumferential wall.

5. The method of claim 4 further comprising:

extending said one or more holes into said second semiconductor substrate.

6. The method of claim 5 whereby said extending said one or more holes into second semiconductor substrate forms a via hole extending through an entire thickness of the second semiconductor substrate.

7. A method of forming a 3D IC comprising the steps of:

bonding a first component to a second component using a bonding layer to form a bonded structure, said first component having a first semiconductor substrate and a first layer with first metallization formed therein, said second component having a second semiconductor substrate that is substantially thinner than the first semiconductor substrate and a second layer with second metallization formed therein, said bonding layer comprised of a first adhesion layer formed on the first layer joined to a second adhesion layer formed on the second layer, and said bonded structure having a periphery;

forming one or more holes through an entire thickness of the second adhesion layer, and an entire thickness of the second layer prior to said bonding step;

filling said one or more holes to form a circumferential wall adjacent to said periphery.

8. The method of claim 7 wherein said second component has an annular region peripheral to an active region and said forming one or more holes through an entire thickness of the second adhesion layer and an entire thickness of the second layer comprises:

forming two or more rows of holes in said annular region, said holes extending generally perpendicular to said second semiconductor substrate and being generally parallel to each other, said holes and rows spaced and extended such that a straight line into said active region and through a) the periphery of said bonding layer or b) the periphery of said second semiconductor substrate necessarily intersects at least one said hole.

9. The method of claim 7, further comprising:

extending said one or more holes into said second semiconductor substrate.

10. The method of claim 9, further comprising:

removing a portion of a back side of the second semiconductor substrate to expose the circumferential wall.