Power electronic control circuitry device

• US 8,862,289 B2
• Filed: 07/27/2011
• Issued: 10/14/2014
• Est. Priority Date: 07/28/2010
• Status: Active Grant

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Fossion, Marc, Durvaux, Marc
• Primary Examiner(s): PATEL, RAMESH B
• Application Number:
  US13/192,408
• Publication Number:
  US 20120197447A1
• Time in Patent Office: 1,175 Days
• Field of Search: 700 19- 21, 700/79, 700/286, 700296-298, 701/1, 701 8- 10, 701 13- 18
• US Class Current: 701/10
• CPC Class Codes: G05B 19/0428 Safety, monitoring G05B19/0423 takes precedence
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A power electronic control circuitry device comprises the following intercommunicating distinct hardware physical entities: a digital microcontroller unit (UNMC) for managing the operation of the device, hardened to withstand the effects of radiations in space; a digital fast regulation unit (UNRR) for controlling priority and real-time processes, hardened to withstand the effects of radiations in space; a digital communication unit (UNC) for communications external to the device, hardened to withstand the effects of radiations in space; a digital tracing and debugging unit (UNTD) for detecting errors in the design of the device; and a digital non-volatile memory (MRN) for storing information representative of the initial configuration of the device, hardened to withstand the effects of radiations in space.

Claims

1. A power electronic control circuitry device comprising the following intercommunicating distinct hardware physical entities:

a digital microcontroller unit for managing the operation of the device, hardened to withstand the effects of radiation in space;

a digital fast regulation unit, operatively coupled to the digital microcontroller unit, for controlling priority and real-time processes, hardened to withstand the effects of radiation in space;

a digital communication unit, operatively coupled to the digital microcontroller unit, for communications external to the device, hardened to withstand the effects of radiation in space;

a digital tracing and debugging unit, operatively coupled to the digital microcontroller unit, the digital fast regulation unit, and the digital communication unit, for detecting errors in the design of the device;

a digital non-volatile memory, operatively coupled to the digital microcontroller unit, the digital fast regulation unit, and the digital communication unit, for storing information representative of the initial configuration of the device, hardened to withstand the effects of radiation in space; and

an assembly comprising a shared memory and means for managing access to said shared memory, for managing the communications according to a mailbox-type mechanism between one hardware physical entity of the device and another hardware physical entity including at least one of the digital microcontroller unit, the digital fast regulation unit, the digital non-volatile memory, and the digital communication unit, of the device, ensuring a physical segregation of said entities and a deterministic behaviour.

2. The device according to claim 1, in which said distinct hardware physical entities further comprise an analogue protection unit, providing temperature, electrical voltage and electrical current protection, to avoid damage to the device and/or to a linked system, wherein the analogue protection unit is resistant to radiation.

3. The device according to claim 1, further comprising non-volatile memory registers, a memory register comprising a dedicated correcting code for improving the resistance to the effects of radiation in space.

4. The device according to claim 3, wherein said access management means are designed to perform a management of said communications in a static and predefined manner in said non-volatile memory registers.

5. The device according to claim 1, wherein said digital rapid regulation, communication, tracing and debugging units and the analogue protection unit comprise finite state machines.

6. The device according to claim 5, wherein said finite state machines are implemented by sequencers executing linear instructions.

7. An aerospace system, comprising at least one device according to claim 1, in which a subset of said units can be made redundant.