Active edge structures providing uniform current flow in insulated gate turn-off thyristors
First Claim
1. An insulated gate turn-off thyristor formed as a die comprising:
- a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type;
a third semiconductor layer of the first conductivity type;
a matrix of cells comprising inner cells and edge cells, wherein each of the inner cells and each of the edge cells comprises a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer;
wherein, in the inner cells, a fourth semiconductor layer of the second conductivity type is formed in first areas between the gate regions near a top surface of the third semiconductor layer, the fourth semiconductor layer having a first concentration profile of dopants of the second conductivity type, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate regions; and
wherein, in at least some of the edge cells, the fourth semiconductor layer having the first concentration profile of dopants of the second conductivity type is not formed in a second area between the gate regions nearest to an outer edge of the edge cells, so as to reduce a current flow near the outer edge of the edge cells,wherein the gate regions do not extend below the third semiconductor layer.
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Accused Products
Abstract
An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n− epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.
7 Citations
19 Claims
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1. An insulated gate turn-off thyristor formed as a die comprising:
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a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a matrix of cells comprising inner cells and edge cells, wherein each of the inner cells and each of the edge cells comprises a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; wherein, in the inner cells, a fourth semiconductor layer of the second conductivity type is formed in first areas between the gate regions near a top surface of the third semiconductor layer, the fourth semiconductor layer having a first concentration profile of dopants of the second conductivity type, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate regions; and wherein, in at least some of the edge cells, the fourth semiconductor layer having the first concentration profile of dopants of the second conductivity type is not formed in a second area between the gate regions nearest to an outer edge of the edge cells, so as to reduce a current flow near the outer edge of the edge cells, wherein the gate regions do not extend below the third semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An insulated gate turn-off thyristor formed as a die comprising:
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a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a matrix of cells comprising inner cells and edge cells, wherein each of the inner cells and each of the edge cells comprises a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; wherein, in the inner cells, a fourth semiconductor layer of the second conductivity type is formed in first areas between the gate regions near a top surface of the third semiconductor layer, the fourth semiconductor layer having a first concentration profile of dopants of the second conductivity type, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate regions; and wherein, in at least some of the edge cells, the fourth semiconductor layer having the first concentration profile of dopants of the second conductivity type is not formed in a second area between the gate regions nearest to an outer edge of the edge cells, so as to reduce a current flow near the outer edge of the edge cells, wherein, in at least some of the inner cells, the fourth semiconductor layer having the first concentration profile of dopants of the second conductivity type is not formed at least in a third area between the gate regions, so as to reduce a current flow through the at least some of the inner cells.
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9. An insulated gate turn-off thyristor formed as a die comprising:
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a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a matrix of cells comprising inner cells and edge cells, wherein each of the inner cells and each of the edge cells comprises a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; wherein, in the inner cells and the edge cells, a fourth semiconductor layer of the second conductivity type is formed in first areas between the gate regions near a top surface of the third semiconductor layer, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate regions; and an electrically insulating first trench extending down to the first semiconductor layer between an outer gate region in the edge cells so as to circumscribe the gate regions in the matrix of cells. - View Dependent Claims (10, 11, 12, 13)
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14. An insulated gate turn-off thyristor formed as a die comprising:
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a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a matrix of cells comprising inner cells and edge cells, wherein each of the inner cells and each of the edge cells comprises a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; wherein, in the inner cells and the edge cells, a fourth semiconductor layer of the second conductivity type is formed in first areas between the gate regions near a top surface of the third semiconductor layer, wherein a vertical structure of NPN and PNP transistors is formed, and conduction between the first semiconductor layer and the fourth semiconductor layer is controlled by a voltage applied to the gate regions; wherein, in at least some of the cells, at least one second area between the gate regions is not a second conductivity type but is part of the third semiconductor layer of the first conductivity type; and a metal electrode electrically contacting the fourth semiconductor layer in the first areas and the third semiconductor layer in the second area to short the first areas to the second area, wherein the gate regions do not extend below the third semiconductor layer. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification