Semiconductor device having switching element and free wheel diode and method for controlling the same

• US 8,890,252 B2
• Filed: 07/26/2011
• Issued: 11/18/2014
• Est. Priority Date: 07/27/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamamoto, Tsuyoshi, Mizuno, Shoji, Sumitomo, Masakiyo, Fujii, Tetsuo, Sakakibara, Jun, Yamaguchi, Hitoshi, Hattori, Yoshiyuki, Kuwahara, Makoto, Saikaku, Hirotaka, Taguchi, Rie
• Primary Examiner(s): Lee, Jae
• Assistant Examiner(s): Mirsalahuddin, Junaiden
• Application Number:
  US13/190,798
• Publication Number:
  US 20120025874A1
• Time in Patent Office: 1,211 Days
• Field of Search: 257/77, 257133-136, 257/365, 257/140, 257260-264, 257/267, 257/327, 257/368, 257341-343, 257330-335, 257/328, 257/E29.199, 257/E27.016, 257/E27.013, 257/E29, 438/29, 438/212, 438/268, 438/270, 438/272, 438/273, 438/294, 438/334, 438/430, 438/431
• US Class Current: 257/368
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7398 with both emitter and collector contacts in the same substrate side
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7819 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Claims

1. A semiconductor device comprising:

a first conductivity type semiconductor layer;

a drift layer having the first conductivity type, arranged on the semiconductor layer, and having an impurity concentration lower than the semiconductor layer;

a base region having a second conductivity type, arranged on the drift layer opposite to the semiconductor layer;

a first conductivity type impurity region arranged on the base region, and having an impurity concentration higher than the drift layer;

a second conductivity type impurity layer arranged at a position deeper than the base region, and contacting the base region;

a trench arranged on a surface of the base region, wherein the trench extends in a longitudinal direction, and the first conductivity type impurity region and the base region are arranged on both sides of the trench;

a gate insulating film arranged on a surface of the trench;

a gate electrode arranged in the trench through the gate insulating film;

a front surface electrode electrically coupled to the first conductivity type impurity region and the base region; and

a back surface electrode arranged on a back surface of the first conductivity type semiconductor layer opposite to the drift layer,

wherein, when a voltage is applied to the gate electrode, an inversion layer is generated in a surface portion of the base region located on a side of the trench,

wherein a current flows between the front surface electrode and the back surface electrode through the first conductivity type impurity region, the inversion layer, and the drift layer so that an inverting vertical semiconductor switching element is provided,

wherein a p-n junction is provided between the base region and the drift layer so that a free wheel diode having a diode operation is provided,

wherein the semiconductor switching element and the free wheel diode are arranged in one chip,

wherein the trench includes a first trench and a second trench,

wherein the first trench is deeper than the base region and reaches the drift layer,

wherein the second trench has a same depth as the first trench, reaches the second conductivity type impurity layer and is shallower than a bottom portion of the second conductivity type impurity layer,

wherein the gate electrode includes a driving gate electrode for driving the vertical semiconductor switching element and a diode gate electrode for generating an inversion layer in the base region at a position where the free wheel diode is arranged,

wherein the driving gate electrode is arranged in the first trench,

wherein the diode gate electrode is arranged in the second trench,

wherein a voltage is independently applied to the driving gate electrode and the diode gate electrode, and

wherein the gate insulating film is between, and directly contacts, the diode gate electrode and the first conductivity type impurity region.

2. The semiconductor device of claim 1,

wherein the second conductivity type impurity layer is a second conductivity type body layer arranged at a lower part of the base region.

3. The semiconductor device of claim 1,

wherein the longitudinal direction of the driving gate electrode is parallel to the longitudinal direction of diode gate electrode, and

wherein the driving gate electrode and the diode gate electrode are arranged in a stripe pattern having a predetermined formation ratio.

4. The semiconductor device of claim 3, further comprising:

a driving gate wiring coupled to the driving gate electrode; and

a diode gate wiring coupled to the diode gate electrode,

wherein the driving gate wiring is drawn from one end of the driving gate electrode in the longitudinal direction, and

wherein the diode gate wiring is drawn from the other end of the diode gate electrode in the longitudinal direction.

5. The semiconductor device of claim 1,

wherein a threshold value in a case where an inversion layer is formed when a voltage is applied to the diode gate electrode is lower than a threshold value in a case where an inversion layer is formed when a voltage is applied to the driving gate electrode.

6. The semiconductor device of claim 1,

wherein the vertical semiconductor switching element is a vertical MOSFET,

wherein the first conductivity type impurity region is a source region,

wherein the front surface electrode is a source electrode, and

wherein the back surface electrode is a drain electrode.

7. A control method for an apparatus including two semiconductor devices connected in series with each other, and an inductive load connected at a junction point between the two semiconductor devices, each of the semiconductor devices comprising:

a first conductivity type semiconductor layer;

a drift layer having the first conductivity type, arranged on the semiconductor layer, and having an impurity concentration lower than the semiconductor layer;

a base region having a second conductivity type, arranged on the drift layer opposite to the semiconductor layer;

a first conductivity type impurity region arranged on the base region, and having an impurity concentration higher than the drift layer;

a second conductivity type impurity layer arranged at a position deeper than the base region, and contacting the base region;

a trench arranged on a surface of the base region, wherein the trench extends in a longitudinal direction, and the first conductivity type impurity region and the base region are arranged on both sides of the trench;

a gate insulating film arranged on a surface of the trench;

a gate electrode arranged in the trench through the gate insulating film;

a front surface electrode electrically coupled to the first conductivity type impurity region and the base region; and

a back surface electrode arranged on a back surface of the first conductivity type semiconductor layer opposite to the drift layer, wherein

when a voltage is applied to the gate electrode, an inversion layer is generated in a surface portion of the base region located on a side of the trench,

a current flows between the front surface electrode and the back surface electrode through the first conductivity type impurity region, the inversion layer, and the drift layer so that an inverting vertical semiconductor switching element is provided,

a p-n junction is provided between the base region and the drift layer so that a free wheel diode having a diode operation is provided,

the semiconductor switching element and the free wheel diode are arranged in one chip,

the trench includes a first trench and a second trench,

the first trench is deeper than the base region and reaches the drift layer,

the second trench has a same depth as the first trench, reaches the second conductivity type impurity layer and is shallower than a bottom portion of the second conductivity type impurity layer,

the gate electrode includes a driving gate electrode for driving the vertical semiconductor switching element and a diode gate electrode for generating an inversion layer in the base region at a position where the free wheel diode is arranged,

the driving gate electrode is arranged in the first trench, and

the diode gate electrode is arranged in the second trench,

the method comprising;

switching the vertical semiconductor switching element in one of the semiconductor devices arranged on a high side from an off state to an on state, and switching the free wheel diode in the other semiconductor device arranged on a low side from an on state to an off state; and

before the vertical semiconductor switching element in the one of semiconductor devices on the high side is switched from the off state to the on state, applying a gate voltage to the diode gate electrode in the other semiconductor device on the low side in order to generate an inversion layer in the base region located on the side of the second trench, in which the diode gate electrode is arranged.