Bus sharing scheme

• US 8,890,600 B1
• Filed: 05/13/2013
• Issued: 11/18/2014
• Est. Priority Date: 07/01/2008
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Timothy J., Kutz, Harold, Thiagarajan, Eashwar, Snyder, Warren S., Hastings, Mark E., Wright, David G.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US13/893,201
• Time in Patent Office: 554 Days
• Field of Search: 327/333, 327/565, 327/564, 326/41, 326/47
• US Class Current: 327/333
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22

Abstract

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.

Claims

1. A programmable device, comprising:

an analog component coupled with a first analog bus of the device;

a digital component coupled with a digital bus of the device; and

a first plurality of IO pads each selectively coupled to at least one analog bus line of a first segment of the first analog bus by a first type of switch and to at least one digital bus line by a second type of switch different from the first type of switch, wherein the first analog bus is configured to selectively couple at least two of the IO pads to each other.

2. The device of claim 1, further comprising a second plurality of IO pads each selectively coupled to at least one analog bus line of a second segment of the first analog bus, wherein the at least one analog bus line of the first analog bus segment is configured to connect to the at least one analog bus line of the second segment of the first analog bus.

3. The device of claim 1, further comprising a second plurality of IO pads each selectively coupled to at least one analog bus line of a second analog bus, wherein at least one bus line of the first analog bus is selectively coupled to at least one bus line of the second analog bus.

4. The device of claim 1, further comprising:

a second plurality of IO pads each selectively coupled to at least one analog bus line of a second analog bus; and

a third analog bus comprising at least one analog bus line selectively coupleable to at least one analog bus line of the first analog bus and to at least one analog bus line of the second analog bus.

5. The device of claim 1, further comprising a second analog bus, wherein each of the first plurality of IO pads is selectively coupled to at least one analog bus line of the second analog bus.

6. The device of claim 1, further comprising a controller configured to dynamically reconfigure the selective coupling of at least one IO pad to the at least one analog bus line.

7. The device of claim 1, wherein the analog component is selected from the group consisting of an ADC, a DAC, a comparator, an internal amplifier and a filter.

8. The device of claim 1, wherein the IO pads are selectively coupled to the at least one analog bus line by an analog switch.

9. The device of claim 1, wherein the IO pads are selectively coupled to the at least one digital bus line by a logic gate.

10. The device of claim 1, wherein at least one IO pad of the plurality of IO pads is selectively coupleable to at least two analog bus lines of the first analog bus.

11. A method of operating a device, comprising:

configuring an analog component to communicate over a first analog bus of the device;

configuring a digital component to communicate over a digital bus of the device;

coupling a first IO pad to a bus line of a first segment of the first analog bus by a first type of switch and to at least one digital bus line by a second type of switch different from the first type of switch; and

coupling a bus line of a second analog bus to the bus line of the first segment of the first analog bus.

12. The method of claim 11, further comprising:

coupling a second IO pad to a bus line of a second segment of the first analog bus; and

coupling the bus line of first segment of the first analog bus to a bus line of the second segment of the first analog bus.

13. The method of claim 11, further comprising coupling a bus line of a third analog bus to the bus line of the segment of the first analog bus.

14. The method of claim 11, further comprising configuring a controller to dynamically reconfigure the coupling of the first IO pad to the bus line of the first analog bus.

15. The method of claim 11, further comprising selecting the function of the analog component from the group consisting of:

and ADC, a DAC, a comparator, internal amplifiers and filters.

16. The method of claim 11, wherein the coupling of the first IO pad to the bus line of the first analog bus comprises configuring an analog switch.

17. The method of claim 11, wherein the coupling of the first IO pad to the bus line of the digital bus comprises configuring a logic gate.

18. A method, comprising:

providing an analog component coupled with a first analog bus of a device;

providing a digital component coupled with a digital bus of the device; and

providing a first plurality of IO pads each selectively coupled to at least one analog bus line of a first segment of the first analog bus by a first type of switch and to at least one digital bus line by a second type of switch different from the first type of switch,

wherein the analog bus is configured to selectively couple at least two of the IO pads to each other.

19. The method of claim 18, further comprising providing a second plurality of IO pads each selectively coupled to at least one analog bus line of a second segment of the first analog bus, wherein at least one bus line of the first analog bus segment is configured to connect to at least one bus line of the second segment of the first analog bus.

20. The method of claim 18, further comprising providing a second analog bus, wherein each of the first plurality of IO pads is selectively coupled to at least one analog bus line of the second analog bus.