Series circuits and devices

• US 8,891,264 B1
• Filed: 11/14/2007
• Issued: 11/18/2014
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Thin Film Electronics ASA
• Inventors: Cleeves, James Montague, Smith, Patrick
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Quddus, Nusrat
• Application Number:
  US11/940,161
• Time in Patent Office: 2,561 Days
• Field of Search: 363/44, 363/52, 363/53, 363/71, 363/76, 363/77, 363/84, 363/89, 363/125, 363/127, 257/223, 257/227, 257/291, 257/292, 257/439, 257/443, 257/655, 438/149, 438/257
• US Class Current: 363/53
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

Embodiments of the present invention relate to a rectifier circuit and methods of making the same for use in wireless devices (e.g., RFID tags). The present invention is drawn to a rectifier circuit comprising first and second diode-wired transistors in series, each having a gate oxide layers of the same target thickness. The first diode-wired transistor receives an alternating current and the second diode-wired transistor provides a rectifier output. The first and second diode-wired transistors are configured to divide between them a first voltage differential across the rectifier circuit. The gate oxides are exposed to a peak stress that is similar to a stress on the gate oxide of logic transistors made using the same process. The present invention is further drawn to a method of making a rectifier circuit, comprising printing a plurality of transistor bodies on a substrate, forming a gate oxide on each of the transistor bodies and a gate on each gate oxide, doping exposed portions of the transistor body to form first and second source/drain terminals therein, and forming interconnects electrically connecting the first source/drain terminals to the gate over the corresponding transistor body.

Claims

1. A rectifier circuit, comprising:

a substrate comprising a member selected from the group consisting of a silicon wafer, a glass plate, a ceramic plate or disc, a plastic sheet or disc, metal foil, a metal sheet or disc, and laminated or layered combinations thereof;

first and second diode-wired thin film metal-oxide-semiconductor transistors (TFTs) in series, each diode-wired TFT having a channel in a patterned semiconductor body on the substrate, and each diode-wired TFT comprising a gate oxide layer on the patterned semiconductor body, and a gate on the gate oxide layer, the gate oxide layer of each diode-wired TFT having a same target thickness,

the first diode-wired TFT receiving an alternating current and providing a first output, and the second diode-wired TFT receiving said first output and providing a rectified output, the first and second diode-wired TFTs configured to divide a first voltage differential across the rectifier circuit; and

third and fourth diode-wired TFTs in series, each of the third and fourth diode-wired TFTs having a channel in a corresponding patterned semiconductor body on the substrate, a gate oxide on the corresponding patterned semiconductor body structurally similar to the gate oxide of the first and second diode-wired TFTs, the third diode-wired TFT receiving a complementary alternating current and providing a second output, the fourth diode-wired TFT receiving said second output and having an output connected to the rectified output, the third and fourth diode-wired TFTs configured to divide a second voltage differential across the rectifier circuit.

2. The rectifier circuit of claim 1, further comprising fifth and sixth diode-wired TFTs in series, each of the fifth and sixth diode-wired TFTs having a corresponding patterned semiconductor body on the substrate, a gate oxide on the corresponding patterned semiconductor body structurally similar to the gate oxide of the first and second diode-wired TFTs, and a gate on the gate oxide layer, coupled between a node complementary to the rectified output and the alternating current, and seventh and eight diode-wired TFTs in series, each of the seventh and eight diode-wired TFTs having a corresponding patterned semiconductor body on the substrate, a gate oxide on the corresponding patterned semiconductor body structurally similar to the gate oxide of the first and second diode-wired TFTs, and a gate on the gate oxide layer, coupled between the node complementary to the rectified output and the complementary alternating current.

3. The rectifier circuit of claim 1, further comprising a plurality of logic TFTs, the logic TFTs comprising a patterned semiconductor body on the substrate, a gate oxide on the patterned semiconductor body, and a gate on the gate oxide layer, wherein the gate oxide of each of the first, second, third and fourth diode-wired TFTs is exposed to a peak stress that is similar to a stress on the gate oxide of the logic TFTs.

4. The rectifier circuit of claim 1, wherein each of the first and second diode-wired TFTs further comprises:

a) first and second source/drain terminals in or on the patterned semiconductor body, the channel being between the first and second source/drain terminals; and

b) an interconnect electrically connecting the first source/drain terminal to the gate.

5. The rectifier circuit of claim 4, wherein the interconnect of the second diode-wired TFT is further connected to the second source/drain terminal of the first diode-wired TFT.

6. The rectifier circuit of claim 1, further comprising first and second capacitors in series, coupled between the alternating current and a complementary alternating current, configured to divide a voltage differential between the alternating current and the complementary alternating current.

7. The rectifier circuit of claim 6, wherein the first and second capacitors each include a dielectric layer having a target thickness equal to the target thickness of the gate oxide of the first and second diode-wired TFTs.

8. The rectifier circuit of claim 6, wherein each of the first and second capacitors comprises:

a) a lower electrode on the substrate, the lower electrode having an extension portion;

b) a dielectric layer on the lower electrode; and

c) an upper electrode on the dielectric layer.

9. The rectifier circuit of claim 8, further comprising a capacitor interconnect electrically connecting the extension portions of each of the first and second capacitors.

10. The rectifier circuit of claim 8, wherein the lower electrode includes a same material and has a same target thickness as the patterned semiconductor body.

11. The rectifier circuit of claim 8, wherein the dielectric layer includes a same material and has the same target thickness as the gate oxide.

12. The rectifier circuit of claim 8, wherein the upper electrode includes a same material and has a same target thickness as a gate of the first and second diode-wired TFTs.

21. An RFID tag, comprising the rectifier circuit of claim 1 and a plurality of logic TFTs.

22. The RFID tag of claim 21, wherein the gate oxides of the first and second diode-wired TFTs are exposed to a peak stress that is similar to a stress on a gate oxide of the logic TFTs.

27. The rectifier circuit of claim 1, wherein the patterned semiconductor body comprises a printed semiconductor body.

29. The rectifier circuit of claim 1, wherein the first and second voltage differentials are the same.

13. A method of making a rectifier circuit, comprising:

a) forming one or more patterned semiconductor bodies on a substrate;

b) forming a gate oxide on the one or more patterned semiconductor bodies for each of a plurality of thin film transistors (TFTs), each gate oxide having a same target thickness, and a gate on each gate oxide, thereby forming the plurality of TFTs;

c) doping exposed portions of the one or more semiconductor bodies to form first and second source/drain terminals for each of the plurality of TFTs;

d) forming interconnects electrically connecting each of the first source/drain terminals to a corresponding gate, thereby forming a plurality of diode-wired TFTs in series, wherein the second source/drain terminal of a first one of the plurality of diode-wired TFTs is electrically connected to the first source/drain terminal of a second one of the plurality of diode-wired TFTs and the second source/drain terminal of a third one of the plurality of diode-wired TFTs is electrically connected to the first source/drain terminal of a fourth one of the plurality of diode-wired TFTs; and

e) configuring (i) the first and third diode-wired TFTs to receive an alternating current and (ii) the second and fourth diode-wired TFTs to provide a rectified output, wherein each of (i) the first and second diode-wired TFTs and (ii) the third and fourth diode-wired TFTs are configured to divide a voltage differential across the rectifier circuit.

14. The method of claim 13, wherein forming the interconnects comprises printing a metal-containing ink on the first source/drain terminals, the gates, and an insulation layer adapted to electrically isolate the first source/drain terminals and the gates.

15. The method of claim 13, further comprising forming first and second capacitors.

16. The method of claim 15, wherein each of the first and second capacitors comprises:

a) a lower electrode on the substrate, the lower electrode having an extension portion;

b) a capacitor dielectric layer on the lower electrode; and

c) an upper electrode on the dielectric layer.

17. The method of claim 16, wherein the capacitor dielectric layer has a same target thickness as that of the gate oxide.

18. The method of claim 16, wherein the lower electrode includes a same material and has a same target thickness as the semiconductor body.

19. The method of claim 16, wherein the upper electrode includes a same material and has a same target thickness at the gate.

20. The method of claim 16, further comprising forming a capacitor interconnect electrically connecting the extension portions of each of the first and second capacitors.

28. The method of claim 13, wherein the second source/drain terminal of the first diode-wired TFT and the first source/drain terminal of the second diode-wired TFT are a common source/drain region of a single patterned semiconductor body.

23. The method of 13, wherein forming said one or more patterned semiconductor bodies comprises printing a plurality of said patterned semiconductor bodies.

24. The method of 13, wherein forming said one or more patterned semiconductor bodies comprises depositing a semiconductor thin film on the substrate and photolithographically patterning said semiconductor thin film.

25. The method of 16, comprising forming said lower electrode substantially simultaneously with said one or more patterned semiconductor bodies, forming said capacitor dielectric layer substantially simultaneously with said gate oxide, and forming said upper electrode substantially simultaneously with said gate.

26. The method of 13, wherein forming said interconnects comprises coating an interconnect metal precursor and locally exposing said interconnect metal precursor to laser radiation.