Nonvolatile semiconductor memory device and memory system

• US 8,891,304 B2
• Filed: 03/03/2011
• Issued: 11/18/2014
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nagashima, Hiroyuki
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US13/039,719
• Publication Number:
  US 20110216592A1
• Time in Patent Office: 1,356 Days
• Field of Search: 365/18.09, 365/185.11, 365/185.17, 365/185.24, 365/185.09, 365/185.01, 365/185.18
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of blocks, each of the plurality of blocks including a plurality of memory strings and a plurality of word lines, each of the plurality of memory strings including serially connected memory cells, one end of the serially connected memory cells is coupled to a bit line through a first select transistor and another end is coupled to a source line through a second select transistor; and

a controller configured to;

read data by applying a first read pass voltage to unselected word lines and applying a read voltage to a selected word line;

before a read operation is performed, apply the first read pass voltage to all of the plurality of word lines to detect an overly programmed memory cell that is not turned on even though the first read pass voltage is applied to its gate; and

when at least one overly programmed memory cell is detected, read data by applying a second read pass voltage to the unselected word lines and applying the read voltage to the selected word line, wherein

the second read pass voltage is higher than the first read pass voltage.

2. The device of claim 1, further comprising a word line driver circuit configured to supply both of the first and second read pass voltages.

3. The device of claim 1, further comprising a bit line control circuit coupled to the bit line and configured to determine whether or not a memory cell connected to the selected word line is turned on.

4. The device of claim 1, wherein the controller is configured to write information, in a redundant area of the block, associated with whether or not the overly programmed memory cell is detected.

5. The device of claim 4, wherein the controller is configured to check the information before reading data from the block.

6. The device of claim 1, wherein the controller is configured to count a number of memory strings in which an overly programmed memory cell is detected and if the number exceeds a threshold value, read data by applying the second read pass voltage to the unselected word lines.

7. The device of claim 1, wherein if the overly programmed memory cell is not detected, the controller is configured to read data by applying the first read pass voltage to the unselected word lines and the read voltage to the selected word line.

8. A memory system comprising:

a nonvolatile semiconductor memory device including a memory cell array, the memory cell array including a plurality of blocks, each of the plurality of blocks including a plurality of memory strings and a plurality of word lines, each of the plurality of memory strings including serially connected memory cells, one end of the serially connected memory cells is coupled to a bit line through a first select transistor and another end is coupled to a source line through a second select transistor; and

a host controller configured to;

read data by applying a first read pass voltage to unselected word lines and applying a read voltage to a selected word line;

before a read operation is performed, apply the first read pass voltage to all of the plurality of word lines to detect an overly programmed memory cell that is not turned on even though the first read pass voltage is applied to its gate; and

when at least one overly programmed memory cell is detected, read data by applying a second read pass voltage to the unselected word lines and applying the read voltage to the selected word line, wherein

the second read pass voltage is higher than the first read pass voltage.

9. The system of claim 8, wherein the nonvolatile semiconductor memory device is configured to output information, to the host controller, associated with whether or not the overly programmed memory cell is detected.

10. The system of claim 8, wherein the nonvolatile semiconductor memory device includes a word line driver circuit configured to supply both of the first and second read pass voltages.

11. The system of claim 8, wherein the nonvolatile semiconductor memory device includes a bit line control circuit coupled to the bit line and configured to determine whether or not a memory cell connected to the selected word line is turned on.

12. The system of claim 8, wherein if the overly programmed memory cell is not detected, the host controller is configured to read data by applying the first read pass voltage to the unselected word lines and the read voltage to the selected word line.