Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV

• US 8,895,440 B2
• Filed: 08/06/2010
• Issued: 11/25/2014
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Choi, DaeSik, Woo, Young Jin, Lee, TaeWoo
• Primary Examiner(s): TAYLOR, EARL N
• Application Number:
  US12/852,433
• Publication Number:
  US 20120032340A1
• Time in Patent Office: 1,572 Days
• Field of Search: 438/675
• US Class Current: 438/675
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing semiconductor material including a plurality of conductive through silicon vias formed through the semiconductor material of the semiconductor wafer;

cutting channels through the semiconductor wafer to provide a plurality of wafer segments including the conductive through silicon vias;

disposing a first semiconductor die over a wafer segment from the plurality of wafer segments;

depositing an encapsulant over the first semiconductor die and wafer segment;

forming a first via through the encapsulant to expose a conductive through silicon via of the wafer segment;

forming a second via through the encapsulant and over a contact pad of the first semiconductor die;

depositing an electrically conductive material in the first and second vias during a same manufacturing step to form a first conductive through mold via extending through the encapsulant to the exposed conductive through silicon via and a second conductive through mold via extending through the encapsulant to the first semiconductor die;

forming a conductive layer over the encapsulant electrically connected to the first and second conductive through mold vias; and

forming an insulating layer over the encapsulant and conductive layer.

2. The method of claim 1, further including forming a plurality of bumps over the wafer segment opposite the first semiconductor die.

3. The method of claim 1, further including;

stacking a second semiconductor die over the wafer segment; and

electrically connecting the first and second semiconductor die through the first and second conductive through mold vias.

4. The method of claim 3, wherein the first and second semiconductor die are different sizes.

5. The method of claim 1, further including:

stacking a second semiconductor die over the wafer segment opposite the first semiconductor die; and

electrically connecting the first and second semiconductor die through the first and second conductive through mold vias.

6. The method of claim 1, further including forming a third conductive through mold via through the channels.

7. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including a plurality of conductive through silicon vias formed through the semiconductor wafer;

cutting a channel through the semiconductor wafer to provide a wafer segment;

disposing a semiconductor die over the wafer segment;

depositing an encapsulant over the semiconductor die and wafer segment;

forming a first conductive through mold via through the encapsulant and over the conductive through silicon vias;

forming a second conductive through mold via through the encapsulant and over a contact pad of the semiconductor die;

forming a conductive layer over the encapsulant and electrically connected to the first and second conductive through mold vias;

forming an insulating layer over the encapsulant and conductive layer; and

forming a third conductive through mold via through the channel.

8. The method of claim 7, further including:

stacking a plurality of semiconductor die over the wafer segment; and

electrically connecting the plurality of semiconductor die through the first and second conductive through mold vias.

9. The method of claim 7, further including:

stacking a plurality of semiconductor die over opposite sides of the wafer segment; and

electrically connecting the plurality of semiconductor die through the first and second conductive through mold vias.

10. The method of claim 7, further including:

stacking an internal stacking module over the semiconductor die; and

electrically connecting the semiconductor die and internal stacking module through the first and second conductive through mold vias.

11. The method of claim 7, further including forming a plurality of bumps over the wafer segment opposite the semiconductor die.

12. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of conductive vias formed through the substrate;

disposing a semiconductor die over the substrate;

depositing an encapsulant over the semiconductor die and substrate;

forming a first via through the encapsulant to expose a conductive via of the substrate;

forming a second via through the encapsulant and over a contact pad of the semiconductor die; and

depositing an electrically conductive material in the first via and second via to form a first conductive through mold via extending through the encapsulant to the exposed conductive via of the substrate and

a second conductive through mold via extending through the encapsulant to the semiconductor die.

13. The method of claim 12, further including:

forming a conductive layer over the encapsulant and electrically connected to the first and second conductive through mold vias; and

forming an insulating layer over the encapsulant and conductive layer.

14. The method of claim 12, further including:

stacking a plurality of semiconductor die over the substrate; and

electrically connecting the plurality of semiconductor die through the first and second conductive through mold vias.

15. The method of claim 14, wherein the plurality of semiconductor die are different sizes.

16. The method of claim 12, further including:

stacking a plurality of semiconductor die over opposite sides of the substrate; and

electrically connecting the plurality of semiconductor die through the first and second conductive through mold vias.

17. The method of claim 12, further including:

stacking an internal stacking module over the semiconductor die; and

electrically connecting the semiconductor die and internal stacking module through the first and second conductive through mold vias.

18. The method of claim 12, further including forming a plurality of bumps over the substrate opposite the semiconductor die.

19. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of conductive vias formed through the substrate;

cutting channels through the substrate to provide a plurality of substrate segments including the conductive vias;

disposing a first semiconductor die over a substrate segment from the plurality of substrate segments;

depositing an encapsulant over the first semiconductor die and substrate segment;

forming a first via through the encapsulant to expose a first conductive via of the substrate segment;

forming a second via through the encapsulant and over a contact pad of the first semiconductor die; and

depositing an electrically conductive material in the first via and second via to form a second conductive via extending through the encapsulant to the exposed first conductive via in the substrate segment and

a third conductive via extending through the encapsulant to the first semiconductor die.

20. The method of claim 19, further including forming a conductive layer over the encapsulant and electrically connected to the second and third conductive vias.

21. The method of claim 19, further including:

stacking a second semiconductor die over the first semiconductor die; and

electrically connecting the first and second semiconductor die through the second and third conductive vias.

22. The method of claim 21, wherein the first and second semiconductor die are different sizes.

23. The method of claim 19, further including:

stacking the first semiconductor die over a first side of the substrate segment;

stacking a second semiconductor die over a second side of the substrate segment; and

electrically connecting the first and second semiconductor die through the second and third conductive vias.