Via structure and via etching process of forming the same

• US 8,896,127 B2
• Filed: 11/08/2012
• Issued: 11/25/2014
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Chiou, Wen-Chih, Yu, Chen-Hua
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/671,711
• Publication Number:
  US 20130062767A1
• Time in Patent Office: 747 Days
• Field of Search: 257/E21.578, 257/E21.585, 257/E23.011, 257/E23.067, 257/741, 257/751, 257/762, 257/773, 257/774, 438/629, 438/637, 438/639, 438/640, 438666-668, 438/672, 438/675, 438/701, 438/713, 438/978
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.

Claims

1. An integrated circuit structure, comprising:

a semiconductor substrate;

a hard mask layer formed on the semiconductor substrate;

at least a conductive layer formed in the hard mask layer; and

a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.

2. The integrated circuit structure of claim 1, wherein the hard mask layer comprises:

an etch stop layer formed on the semiconductor substrate; and

a first dielectric layer formed on the etch stop layer,

wherein the conductive layer formed in the hard mask layer is a contact structure.

3. The integrated circuit structure of claim 2, wherein the etch stop layer comprises silicon nitride.

4. The integrated circuit structure of claim 1, wherein the hard mask layer comprises:

an etch stop layer formed on the semiconductor substrate;

a first dielectric layer formed on the etch stop layer; and

a second dielectric layer formed on the first dielectric layer,

wherein the conductive layer formed in the hard mask layer is an interconnect structure.

5. The integrated circuit structure of claim 1, wherein the via is filled with a conductive material.

6. The integrated circuit structure of claim 5, wherein the conductive material is copper.

7. The integrated circuit structure of claim 5, wherein the conductive material protrudes beyond the hard mask layer opposite the semiconductor substrate.

8. The integrated circuit structure of claim 5, further comprising an insulating material between sidewalls of the conductive material and sidewalls of the via.

9. The integrated circuit structure of claim 8, wherein a portion of the sidewalls of the conductive material are exposed by the insulating material.

10. The integrated circuit structure of claim 1, further comprising an inter-metal dielectric over the hard mask layer.

11. An integrated circuit structure, comprising:

a semiconductor substrate;

a hard mask layer formed on the semiconductor substrate;

a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall;

a conductive material disposed in the via; and

an insulating material between sidewalls of the conductive material and sidewalls of the via.

12. The integrated circuit structure of claim 11, wherein the insulating material is between a bottom of the via and the conductive material.

13. The integrated circuit structure of claim 12, wherein a portion of the sidewalls of the conductive material are exposed by the insulating material.

14. The integrated circuit structure of claim 12, wherein an entirety of the sidewalls of the conductive material are covered by the conductive material.

15. The integrated circuit of claim 12, further comprising a device formed in the hard mask layer.

16. The integrated circuit of claim 15, further comprising an interconnect structure formed in the hard mask layer.

17. An integrated circuit structure, comprising:

a semiconductor substrate;

a hard mask layer formed on the semiconductor substrate;

a conductive contact extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the conductive contact has a round corner and a tapered sidewall; and

an insulating material between sidewalls of the conductive contact and the semiconductor substrate.

18. The integrated circuit structure of claim 17, wherein the hard mask layer comprises

a contact etch stop layer on the semiconductor substrate;

and

an inter-level dielectric on the contact etch stop layer.

19. The integrated circuit structure of claim 17, further comprising an adhesion promoting layer between the conductive contact and the insulating layer.

20. The integrated circuit structure of claim 17, wherein a top portion of the conductive contact is free of the insulating layer.