Transaction processing using multiple protocol engines

• US 8,898,254 B2
• Filed: 09/09/2013
• Issued: 11/25/2014
• Est. Priority Date: 11/05/2002
• Status: Expired due to Fees

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Memory Integrity LLC
• Inventors: Kota, Rajesh, Watson, JR., Charles Edward, Glasco, David Brian
• Primary Examiner(s): Nguyen, Tammy
• Application Number:
  US14/021,984
• Publication Number:
  US 20140013079A1
• Time in Patent Office: 442 Days
• Field of Search: 709/212, 709/238, 370/230, 370/474, 370/235, 370/338, 370/352
• US Class Current: 709/217
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Abstract

A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Claims

1. A cluster, comprising:

a plurality of processing nodes; and

an interconnection controller coupled to the plurality of processing nodes, the interconnection controller including a plurality of protocol engines configured to process memory transactions in accordance with a cache coherence protocol, wherein each protocol engine of said plurality of protocol engines is configured to be assigned a distinct subset of a global memory space, the plurality of protocol engines further comprising;

(a) a first protocol engine configured to be assigned a first subset of the global memory space, said first subset of the global memory space corresponding to one of local and remote memory; and

(b) a second protocol engine configured to be assigned a second subset of the global memory space, said second subset of the global memory space corresponding to one of local and remote memory;

wherein the cluster further comprises circuitry configured to select the first protocol engine of the protocol engines using destination information associated with a memory transaction of the memory transactions where the destination information corresponds to the first subset of the global memory space and wherein the circuitry is configured to select the second protocol engine where the destination information corresponds to the second subset of the global memory space.

2. The cluster of claim 1, wherein the processing nodes and interconnection controller are interconnected in a point-to-point architecture.

3. The cluster of claim 2, wherein the point-to-point architecture comprises a ring topology.

4. The cluster of claim 2, wherein the point-to-point architecture comprises a mesh topology.

5. The cluster of claim 2, wherein the destination information associated with the ˜

memory transaction comprises a target address corresponding to one or more packets associated with the memory transaction.

6. The cluster of claim 5, wherein the circuitry is contained in at least one of said plurality of processing nodes and said circuitry is further configured to forward at least one of said one or more packets to a selected the first one or more protocol engines of the plurality of protocol engines with reference to at least one bit of the target address.

7. The cluster of claim 5, wherein the interconnection controller further comprises a protocol engine configured to process interrupts.

8. The cluster of claim 1, wherein the interconnection controller is further configured such that the second subset of the global memory space is mutually exclusive of the first subset of the global memory space.