Integrated circuit device with well controlled surface proximity and method of manufacturing same

• US 8,900,960 B2
• Filed: 08/07/2013
• Issued: 12/02/2014
• Est. Priority Date: 06/16/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Ming-Huan, Cheng, Chun-Fai, Ouyang, Hui, Chiu, Yuan-Hung, Chen, Yen-Ming
• Primary Examiner(s): Coleman, William D
• Application Number:
  US13/961,748
• Publication Number:
  US 20130323891A1
• Time in Patent Office: 482 Days
• Field of Search: 438/302, 438/300
• US Class Current: 438/300
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Claims

1. A method comprising:

forming a gate structure over a semiconductor substrate;

performing a first implantation process with a first dopant on the substrate, thereby forming a lightly doped source and drain (LDD) region in the substrate, the LDD region being interposed by the gate structure;

performing a second implantation process with a second dopant on the substrate by performing a tilt-angle ion implantation process, the second dopant being opposite the first dopant, thereby forming a doped region in the substrate, the doped region being interposed by the gate structure and spaced a distance from the gate structure; and

after performing the first and second implantation processes, forming source and drain features on each side of the gate structure, wherein forming the source and drain features includes performing a first etching process and a second etching process to the semiconductor substrate to form a recess that defines a source and drain region in the semiconductor substrate, wherein the first etching process is different than the second etching process.

2. The method of claim 1 wherein:

the performing the first implantation process with the first dopant includes utilizing a p-type dopant; and

the performing the second implantation process with the second dopant includes utilizing an n-type dopant.

3. The method of claim 1 wherein the performing the second implantation process includes:

before the second implantation process, forming a dielectric layer over the substrate, including over the gate structure;

utilizing the dielectric layer as a mask during the second implantation process, wherein the doped region spaced the distance away from the gate structure is a thickness of the dielectric layer along sidewalls of the gate structure; and

thereafter, utilizing the dielectric layer to form the spacers.

4. The method of claim 1 wherein the method includes:

before the second implantation process, forming offset spacers along sidewalls of the gate structure.

5. The method of claim 1 wherein the forming the source and drain features on each side of the gate structure includes:

epitaxially (epi) growing a semiconductor material to fill the recess.

6. The method of claim 1, wherein the first etching process includes a dry etching process and the second etching process includes a wet etching process.

7. The method of claim 5 wherein performing the first etching process and the second etching process to the semiconductor substrate to form the recess includes at least one of etching a first and second facet in a {111} crystallographic plane of the substrate and etching a third facet in a {100} crystallographic plane of the substrate.

8. The method of claim 5 wherein performing the first etching process and the second etching process to the semiconductor substrate to form the recess includes etching the substrate such that a top surface of the substrate extends a distance from a sidewall of the gate structure to the recess, the distance being about 1 nm to about 3 nm.

9. The method of claim 7 wherein the etching the first, second, and third facets includes:

etching an angle of about 45.0°

to about 80.0°

between the first and second facets; and

etching an angle of about 50.0°

to about 70.0°

between the second and third facets.

10. The method of claim 7 wherein performing the first etching process and the second etching process to the semiconductor substrate to form the recess includes etching the substrate such that a distance between a top surface of the substrate and an intersection of the first and second facets is about 5 nm to about 10 nm.

11. A method comprising:

forming a gate structure over a substrate;

implanting a first dopant on the substrate, thereby forming a lightly doped source and drain (LDD) region in the substrate, the LDD region being interposed by the gate structure;

implanting a second dopant on the substrate by performing a tilt-angle ion implantation process to form a doped region;

forming a spacer on a sidewall of the gate structure, wherein the doped region extends within the substrate directly under the spacer; and

forming source and drain features on the substrate, the source and drain features being interposed by the gate structure, wherein forming the source and drain features includes removing a portion of the doped region such that the doped region no longer extends within the substrate directly under the spacer.

12. The method of claim 11 wherein one of the first and the second dopants includes a p-type dopant and the other one of the first and the second dopants includes an n-type dopant.

13. The method of claim 11 wherein the doped region doped with the second dopant is spaced a distance away from the gate structure.

14. The method of claim 11 wherein forming the source and drain features on the substrate includes:

removing at least a portion of the substrate at least a side of the gate structure, thereby forming a recess in the substrate; and

epitaxially (epi) growing a semiconductor material on the recess, thereby forming the source and drain features.

15. The method of claim 13 wherein the method includes:

forming a dielectric layer over the substrate and over the gate structure; and

implanting the second dopant utilizing the dielectric layer as a mask.

16. The method of claim 15 wherein the distance is substantially the same with a thickness of the dielectric layer formed along at least the sidewall of the gate structure.

17. The method of claim 15 wherein the method further includes forming another spacer utilizing the dielectric layer.

18. The method of claim 14 wherein the recess defines a source and drain region in the substrate.

19. The method of claim 14 wherein the forming the recess in the substrate further includes, at least one of etching a first and second facet in a {111} crystallographic plane of the substrate and etching a third facet in a {100} crystallographic plane of the substrate.

20. The method of claim 19 wherein the etching the first and the second facets includes etching an angle of about 45.0°

to about 80.0°

between the first and second facets.

21. The method of claim 19 wherein the etching the third facet includes etching an angle of about 50.0°

to about 70.0°

between the second and third facets.