Dual frequency crystal oscillator

• US 8,902,529 B1
• Filed: 11/20/2012
• Issued: 12/02/2014
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Bennett, George J.
• Primary Examiner(s): HOLDER, REGINA NEAL
• Application Number:
  US13/682,686
• Time in Patent Office: 742 Days
• Field of Search: None
• US Class Current: 360/51
• CPC Class Codes: G11B 20/1024 wherein a phase-locked loop [PLL] is used
• CPC Class Codes: G11B 5/59616 Synchronisation; Clocking G11B5/59622 takes precedence
• CPC Class Codes: H03B 1/00 Details
• CPC Class Codes: H03B 2200/0064 Pulse width, duty cycle or on/off ratio
• CPC Class Codes: H03B 5/36 active element in amplifier being semiconductor device H03B5/323, H03B5/326 , H03B5/38 take precedence

Abstract

An oscillator is disclosed comprising a first crystal operable to generate a first oscillating signal at a first frequency, and a second crystal coupled to the first crystal and operable to generate a second oscillating signal at a second frequency higher than the first frequency. The oscillator further comprises a DC restore circuit operable to generate a third oscillating signal comprising a substantially fifty percent duty cycle in response to the second oscillating signal.

Claims

1. An oscillator comprising:

a first crystal operable to generate a first oscillating signal at a first frequency;

a second crystal coupled to the first crystal and operable to generate a second oscillating signal in response to the first oscillating signal at a second frequency higher than the first frequency; and

a DC restore circuit operable to generate a third oscillating signal comprising a substantially fifty percent duty cycle in response to the second oscillating signal.

2. The oscillator as recited in claim 1, wherein the first and second crystals are fabricated in a single package.

3. The oscillator as recited in claim 1, further comprising:

a first amplifier coupled to the first crystal and operable to generate the first oscillating signal; and

a second amplifier coupled to the second crystal and operable to generate the second oscillating signal,

wherein the first amplifier comprises a first DC offset and the second amplifier comprises a second DC offset different from the first DC offset.

4. The oscillator as recited in claim 3, wherein the DC restore circuit is operable to compensate for the difference between the first DC offset and the second DC offset.

5. The oscillator as recited in claim 4, wherein the DC restore circuit is operable to compensate for the difference between the first DC offset and the second DC offset by adding a bias signal to an input of the second amplifier.

6. The oscillator as recited in claim 5, wherein the DC restore circuit is operable to:

first count a number of cycles of a fast clock while the second oscillating signal is above a threshold;

second count a number of cycles the fast clock while the second oscillating signal is below the threshold; and

generate the third oscillating signal based on a difference between the first count and the second count.

7. The oscillator as recited in claim 6, wherein the DC restore circuit is operable to generate the bias signal based on the difference between the first count and the second count.

8. The oscillator as recited in claim 1, wherein the DC restore circuit is operable to:

first count a number of cycles of a fast clock while the second oscillating signal is above a threshold;

second count a number of cycles the fast clock while the second oscillating signal is below the threshold; and

generate the third oscillating signal based on a difference between the first count and the second count.

9. The oscillator as recited in claim 1, wherein the second crystal acts as a bandpass filter for extracting a harmonic frequency component of the first oscillating signal.

10. A disk drive comprising:

a disk;

a head actuated over the disk;

a pulse width modulated (PWM) signal generator operable to generate a PWM signal;

a spindle motor operable to rotate the disk in response to the PWM signal;

a phase-locked loop (PLL) operable to generate a system clock used to process a read signal emanating from the head; and

an oscillator comprising;

a first crystal operable to generate a first oscillating signal at a first frequency; and

a second crystal coupled to the first crystal and operable to generate a second oscillating signal at a second frequency higher than the first frequency,

wherein;

the PWM signal generator is operable to generate the PWM signal based on the first oscillating signal; and

the PLL is operable to generate the system clock based on the second oscillating signal.

11. The disk drive as recited in claim 10, wherein the first and second crystals are fabricated in a single package.

12. A method comprising:

generating a first oscillating signal at a first frequency using a first crystal;

generating a second oscillating signal in response to the first oscillating signal at a second frequency higher than the first frequency using a second crystal coupled to the first crystal; and

generating a third oscillating signal comprising a substantially fifty percent duty cycle in response to the second oscillating signal.

13. The method as recited in claim 12, wherein the first and second crystals are fabricated in a single package.

14. The method as recited in claim 13, further comprising:

generating the first oscillating signal using a first amplifier coupled to the first crystal; and

generating the second oscillating signal using a second amplifier coupled to the second crystal,

wherein the first amplifier comprises a first DC offset and the second amplifier comprises a second DC offset different from the first DC offset.

15. The method as recited in claim 14, further comprising generating the third oscillating signal by compensating for the difference between the first DC offset and the second DC offset.

16. The method as recited in claim 15, further comprising compensating for the difference between the first DC offset and the second DC offset by adding a bias signal to an input of the second amplifier.

17. The method as recited in claim 16, further comprising:

first counting a number of cycles of a fast clock while the second oscillating signal is above a threshold;

second counting a number of cycles the fast clock while the second oscillating signal is below the threshold; and

generating the third oscillating signal based on a difference between the first count and the second count.

18. The method as recited in claim 17, further comprising generating the bias signal based on the difference between the first count and the second count.

19. The method as recited in claim 12, further comprising:

first counting a number of cycles of a fast clock while the second oscillating signal is above a threshold;

second counting a number of cycles the fast clock while the second oscillating signal is below the threshold; and

generating the third oscillating signal based on a difference between the first count and the second count.

20. The method as recited in claim 12, wherein the second crystal acts as a bandpass filter for extracting a harmonic frequency component of the first oscillating signal.

21. A method of operating a disk drive, the disk drive comprising a head actuated over a disk, a pulse width modulated (PWM) signal generator operable to generate a PWM signal, a spindle motor operable to rotate the disk in response to the PWM signal, and a phase-locked loop (PLL) operable to generate a system clock used to process a read signal emanating from the head, the method comprising:

generating a first oscillating signal at a first frequency using a first crystal; and

generating a second oscillating signal at a second frequency higher than the first frequency using a second crystal coupled to the first crystal,

wherein;

the PWM signal generator is operable to generate the PWM signal based on the first oscillating signal; and

the PLL is operable to generate the system clock based on the second oscillating signal.

22. The method as recited in claim 21, wherein the first and second crystals are fabricated in a single package.