Nonvolatile memory device providing negative voltage

• US 8,902,655 B2
• Filed: 05/03/2012
• Issued: 12/02/2014
• Est. Priority Date: 07/06/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Shim, Sang-Won, Kwak, Pan-Suk, Park, Ki-Tae, Choi, Yoon-Hee
• Primary Examiner(s): Hur, J. H.
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US13/463,063
• Publication Number:
  US 20130010539A1
• Time in Patent Office: 943 Days
• Field of Search: 365/185.11, 365/189.11, 365/230.06, 365/185.18, 365/185.27, 365/185.12
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A nonvolatile memory device including memory blocks, a pre-decoder, and a row decoder is disclosed. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

Claims

1. A nonvolatile memory device comprising:

memory blocks, each of the memory blocks having a plurality of memory cells;

address buffers configured to output address signals;

a pre-decoder including;

a multiplexer configured to generate multiplexing signals in response to the address signals; and

negative level shifters, each of the negative level shifters configured to generate a converted multiplexing signal corresponding to a multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage; and

a row decoder configured to generate a block selecting signal by decoding the converted multiplexing signal, and to select at least one of the memory blocks in response to the block selecting signal.

2. The nonvolatile memory device of claim 1, wherein the memory blocks and the row decoder are disposed in a memory cell core region, and wherein the pre-decoder is disposed in a peripheral region different from the memory cell core region.

3. The nonvolatile memory device of claim 1, wherein each of the negative level shifters is configured to convert a multiplexing signal having a power supply voltage into a converted multiplexing signal having the power supply voltage.

4. The nonvolatile memory device of claim 3, wherein each of the negative level shifters comprises:

a PMOS transistor connected between a power supply terminal supplied with the power supply voltage and an output terminal and configured to receive the multiplexing signal having the power supply voltage and to output the converted multiplexing signal having the power supply voltage to the output terminal; and

an NMOS transistor connected between the output terminal and a negative voltage terminal supplied with the first negative voltage and configured to receive the multiplexing signal having the ground voltage and to output the converted multiplexing signal having the first negative voltage to the output terminal,

wherein a body terminal of the NMOS transistor is connected to the negative voltage terminal.

5. The nonvolatile memory device of claim 1, wherein the row decoder comprises:

decoding units, each of the decoding units corresponding to a memory block, configured to generate the block selecting signal to select at least one of the memory blocks in response to at least two of the converted multiplexing signals.

6. The nonvolatile memory device of claim 5, wherein each of the decoding units comprises:

a combinational logic circuit configured to generate a voltage transfer enable signal in response to the at least two converted multiplexing signals, the voltage transfer enable signal having one of the power supply voltage and the first negative voltage;

a pull-up circuit configured to provide a high voltage higher than the power supply voltage to the block selecting signal when the voltage transfer enable signal has the power supply voltage;

a pull-down circuit configured to provide the first negative voltage to the block selecting signal when the voltage transfer enable signal has the first negative voltage; and

a voltage transfer circuit configured to transfer voltages of selection lines to the word lines of a corresponding memory block in response to the block selecting signal.

7. The nonvolatile memory device of claim 5, further comprising:

word lines connected to the plurality of memory cells; and

a selection line decoder configured to provide voltages to the word lines in response to the block selecting signal.

8. The nonvolatile memory device of claim 7, wherein a well of each of the decoding units is connected to a negative voltage terminal, and the first negative voltage is supplied to the negative voltage terminal when a second negative voltage is supplied to at least one of the word lines of the selected memory block.

9. The nonvolatile memory device of claim 8, further configured such that a voltage of the negative voltage terminal of the decoding unit corresponding to the selected memory block is lowered to the first negative voltage after a first delay time when the converted multiplexing signal transit to the first negative voltage and is increased up to the ground voltage before a second delay time when the converted multiplexing signal is increased to the ground voltage from the first negative voltage.

10. The nonvolatile memory device of claim 8, wherein the second negative voltage for at least one of the word lines is identical to or higher than the first negative voltage.

11. A memory device comprising:

a memory cell array including one or more memory blocks, each of the one or more memory bocks having a plurality of memory cell transistors;

word lines connected to the plurality of memory cell transistors;

first address buffers configured to output first address signals;

second address buffers configured to output second address signals;

a selection line decoder configured to generate selection line signals in response to the first address signals;

a pre-decoder including;

a multiplexer configured to generate multiplexing signals in response to the second address signals; and

negative level shifters, each of the negative level shifters configured to generate a converted multiplexing signal corresponding to a multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a negative voltage; and

a row decoder configured to generate a block selecting signal by decoding the converted multiplexing signal, and to select at least one of the word lines in response to the block selecting signal and the selection line signals.

12. The memory device of the claim 11, wherein the memory cell array and the row decoder are disposed in a memory cell core region, and wherein the pre-decoder is disposed in a peripheral region different from the memory cell core region.

13. The memory device of claim 11, wherein a level of each of the multiplexing signals is a ground voltage or a power supply voltage, and wherein a level of each of the converted multiplexing signals is the negative voltage or the power supply voltage.

14. The memory device of claim 11, wherein the row decoder comprises:

a block selection circuit configured to generate the block selecting signal to select at least one block of the one or more memory blocks in response to the converted multiplexing signals; and

a voltage transfer circuit configured to transfer the selection line signals to corresponding word lines of the selected memory block.

15. The memory device of claim 14, wherein the block selecting signal has the negative voltage or a higher voltage greater than a power supply voltage.

16. The memory device of claim 15, wherein the each of the negative level shifters comprises:

a PMOS transistor connected between a power supply terminal supplied with the power supply voltage and an output terminal and configured to receive the multiplexing signal having the power supply voltage and to output the converted multiplexing signal having the power supply voltage to the output terminal; and

an NMOS transistor connected between the output terminal and a negative voltage terminal supplied with the negative voltage and configured to receive the multiplexing signal having the ground voltage and to output the converted multiplexing signal having the negative voltage to the output terminal,

wherein a body terminal of the NMOS transistor is connected to the negative voltage terminal.

17. A nonvolatile memory device comprising:

a first mat having first memory blocks;

a second mat having second memory blocks;

address buffers configured to output first and second address signals; and

a pre-decoder including;

a first multiplexer and a second multiplexer configured to generate first and second pre-decoding signals in response to the first and second address signals, respectively;

first negative level shifters, each of the first negative level shifters configured to generate a first converted pre-decoding signal corresponding to a respective first pre-decoding signal by converting a first pre-decoding signal having a ground voltage into a first converted pre-decoding signal having a negative voltage; and

second negative level shifters, each of the second negative level shifters configured to generate a second converted pre-decoding signal corresponding to a respective second pre-decoding signal by converting a second pre-decoding signal having the ground voltage into a second converted pre-decoding signal having the negative voltage;

a first row decoder configured to select one of the first memory blocks in response to the first converted pre-decoding signals; and

a second row decoder configured to select one of the second memory blocks in response to the second converted pre-decoding signals.

18. The memory device of the claim 17, wherein the first and second memory blocks and the first and second row decoders are disposed in a memory cell core region, and wherein the first and second pre-decoders are disposed in a peripheral region different from the memory cell core region.

19. The nonvolatile memory device of claim 17, further comprising:

a well voltage selecting switch circuit configured to switch the negative voltage into a well of the first row decoder or a well of the second row decoder;

a selection line selecting switch circuit configured to switch voltage to be supplied to selection lines into first selection lines corresponding to the first row decoder or second selection lines corresponding to the second row decoder;

a selection line decoder configured to transfer a selection word line voltage and non-selection word line voltages to the selection lines;

a word line voltage selecting switch circuit configured to select one of a program voltage and a read verification voltage as the selection word line voltage; and

a read verification voltage selecting switch circuit configured to select one of a first voltage and the negative voltage for a word line as the read verification voltage,

wherein when the negative voltage is supplied to a selected word line, the negative voltage is supplied to a well of the well voltage selecting switch circuit, a well of the selection line selecting switch circuit, a well of the selection line decoder, a well of the word line voltage selecting switch circuit, and a well of the read verification voltage selecting switch circuit.

20. The nonvolatile memory device of claim 19, further comprising:

a negative voltage generator configured to generate the negative voltage identical in level to the negative voltage for a word line voltage.