Battery pack monitoring system and method for assigning a binary ID to a microprocessor in the battery pack monitoring system

• US 8,904,049 B2
• Filed: 08/23/2012
• Issued: 12/02/2014
• Est. Priority Date: 08/23/2012
• Status: Active Grant

• Current Assignee: LG Energy Solution Limited (LG Corporation)
• Original Assignee: LG Chem Limited (LG Corporation)
• Inventors: McCormick, Richard
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US13/592,980
• Publication Number:
  US 20140059260A1
• Time in Patent Office: 831 Days
• Field of Search: 710/9, 710/10, 710/110, 710/305, 710/313, 320/134, 429/61
• US Class Current: 710/9
• CPC Class Codes: B60L 2240/545 Temperature
• CPC Class Codes: B60L 2240/547 Voltage
• CPC Class Codes: B60L 58/21 having the same nominal voltage
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0047 with monitoring or indicating devices or circuits
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries
• CPC Class Codes: Y02T 90/16 Information or communication technologies improving the operation of electric vehicles

Abstract

A battery pack monitoring system is provided. The system includes a master microprocessor and a first microprocessor. The master microprocessor outputs a first signal from an output port thereof to induce an input port of the first microprocessor to have a first low logic voltage. The master microprocessor sends a message having a first binary ID from the communication bus port thereof through a communication bus after outputting the first signal. The first microprocessor receives the first binary ID at the communication bus port thereof and stores the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage.

Claims

1. A battery pack monitoring system, comprising:

a master microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the master microprocessor operably coupled to a communication bus;

a first microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the first microprocessor operably coupled to the communication bus;

a second microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the second microprocessor operably coupled to the communication bus;

a first over-voltage protection circuit electrically coupled between the output port of the master microprocessor and the input port of the first microprocessor;

a second over-voltage protection circuit electrically coupled between the output port of the first microprocessor and the input port of the second microprocessor;

the master microprocessor configured to output a first signal from the output port thereof to induce the input port of the first microprocessor to have a first low logic voltage, the master microprocessor further configured to send a message having a first binary ID from the communication bus port thereof through the communication bus after outputting the first signal; and

the first microprocessor configured to receive the first binary ID at the communication bus port thereof and to store the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage.

2. The battery pack monitoring system of claim 1, wherein the first microprocessor further configured to send a confirmation message from the communication bus port thereof through the communication bus to the communication bus port of the master microprocessor after storing the first binary ID in the non-volatile memory of the first microprocessor.

3. The battery pack monitoring system of claim 2, wherein:

the first microprocessor further configured to output a second signal from the output port thereof to induce the input port of the second microprocessor to have a second low logic voltage after storing the first binary ID;

the master microprocessor further configured to send a message having a second binary ID from the communication bus port thereof through the communication bus after receiving the confirmation message from the first microprocessor; and

the second microprocessor configured to receive the second binary ID at the communication bus port thereof and to store the second binary ID in a non-volatile memory of the second microprocessor when the input port of the second microprocessor has the second low logic voltage.

4. The battery pack monitoring system of claim 3, wherein the second microprocessor further configured to send a confirmation message from the communication bus port thereof through the communication bus to the communication bus port of the master microprocessor after storing the second binary ID in the non-volatile memory of the second microprocessor.

5. The battery pack monitoring system of claim 4, further comprising:

a third microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the third microprocessor operably coupled to the communication bus;

a third over-voltage protection circuit electrically coupled between the output port of the second microprocessor and the input port of the third microprocessor;

the second microprocessor further configured to output a third signal from the output port thereof to induce the input port of the third microprocessor to have a third low logic voltage after the input port of the second microprocessor has the second low logic voltage;

the master microprocessor further configured to send a message having a third binary ID from the communication bus port thereof through the communication bus after receiving the confirmation message from the second microprocessor; and

the third microprocessor configured to receive the third binary ID at the communication bus port thereof and to store the third binary ID in a non-volatile memory of the third microprocessor when the input port of the third microprocessor has the third low logic voltage.

6. The battery pack monitoring system of claim 5, wherein the third microprocessor further configured to send a confirmation message from the communication bus port thereof through the communication bus to the communication bus port of the master microprocessor after storing the third binary ID in the non-volatile memory of the third microprocessor.

7. The battery pack monitoring system of claim 6, wherein the third microprocessor further configured to output a fourth signal from the output port thereof to induce the input port of the master microprocessor to have a fourth low logic voltage after the input port of the third microprocessor has the third low logic voltage.

8. The battery pack monitoring system of claim 1, wherein the first over-voltage protection circuit comprises:

a zener diode electrically coupled between the input port of the first microprocessor and electrical ground such that the zener diode limits a voltage amplitude applied to the input port of the first microprocessor to less than a predetermined voltage level;

a capacitor electrically coupled between the input port of the first microprocessor and electrical ground; and

a resistor electrically coupled between the input port of the first microprocessor and the output port of the master microprocessor.

9. The battery pack monitoring system of claim 1, wherein:

the master microprocessor further configured to send a command message having a measurement command and the first binary ID from the communication bus port thereof through the communication bus to the communication bus port of the first microprocessor; and

the first microprocessor further configured to send a measurement message having at least one measured value associated with a battery module from the communication bus port of the first microprocessor through the communication bus to the communication bus port of the master microprocessor, in response to receiving the command message.

10. A method for assigning a binary ID to a microprocessor in a battery pack monitoring system, the battery pack monitoring system having a master microprocessor with an input port, an output port, and a communication bus port, the communication bus port of the master microprocessor operably coupled to a communication bus;

the battery pack monitoring system further having a first microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the first microprocessor operably coupled to the communication bus;

the battery pack monitoring system further having a second microprocessor having an input port, an output port, and a communication bus port, the communication bus port of the second microprocessor operably coupled to the communication bus;

the battery pack monitoring system further having a first over-voltage protection circuit electrically coupled between the output port of the master microprocessor and the input port of the first microprocessor;

the battery pack monitoring system further having a second over-voltage protection circuit electrically coupled between the output port of the first microprocessor and the input port of the second microprocessor;

the method comprising;

outputting a first signal from the output port of the master microprocessor to induce the input port of the first microprocessor to have a first low logic voltage;

sending a message having a first binary ID from the communication bus port of the master microprocessor through the communication bus after generating the first signal; and

receiving the first binary ID at the communication bus port of the first microprocessor, and

storing the first binary ID in a non-volatile memory of the first microprocessor when the input port of the first microprocessor has the first low logic voltage.

11. The method of claim 10, further comprising:

sending a command message having a measurement command and the first binary ID from the communication bus port of the master microprocessor through the communication bus to the communication bus port of the first microprocessor; and

sending a measurement message having at least one measured value associated with a battery module from the communication bus port of the first microprocessor through the communication bus to the communication bus port of the master microprocessor, in response to receiving the command message.