Electronic device packages having bumps and methods of manufacturing the same

• US 8,907,487 B2
• Filed: 09/14/2012
• Issued: 12/09/2014
• Est. Priority Date: 06/13/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Chung, Qwan Ho, Nam, Jong Hyun, Kim, Si Han, Lee, Sang Yong, Kim, Seung Jee, Shin, Seong Cheol
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US13/618,813
• Publication Number:
  US 20130334683A1
• Time in Patent Office: 816 Days
• Field of Search: None
• US Class Current: 257/773
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/02333 being a bump
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03334 using a preform
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/03472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/03474 Multilayer masks
• CPC Class Codes: H01L 2224/03903 using different masks
• CPC Class Codes: H01L 2224/03906 with modification of the same mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 : the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/11602 : Mechanical treatment, e.g. polishing, grinding
• CPC Class Codes: H01L 2224/1184 : involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Claims

1. An electronic device package comprising:

a semiconductor chip mounted on a bottom dielectric layer;

a bump having a post disposed on a contact portion of the semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post;

a dielectric layer embedding the semiconductor chip and exposing the enlarged portion of the bump and an upper sidewall of the post; and

an interconnection portion formed on the dielectric layer and having a locking portion and a connection portion,

wherein the locking portion penetrates a portion of the dielectric layer to substantially surrounds the enlarged portion of the bump and the upper sidewall of the post and the connecting portion is formed on a surface of the dielectric layer and is extended from the locking portion to serve as a circuit interconnection line.

2. The electronic device package of claim 1, wherein the bump including the post and the enlarged portion have a substantially hammer-shaped configuration.

3. The electronic device package of claim 1, wherein the bump includes a first metal material and the locking portion of the interconnection portion includes a second metal material different from the first metal material.

4. The electronic device package of claim 1, wherein the bump includes gold or copper and the locking portion of the interconnection portion includes copper.

5. The electronic device package of claim 1, further comprising:

a through via penetrating the dielectric layer and the bottom dielectric layer and connecting to the interconnection portion.