Semiconductor wafer bonding incorporating electrical and optical interconnects

• US 8,912,017 B2
• Filed: 05/03/2012
• Issued: 12/16/2014
• Est. Priority Date: 05/10/2011
• Status: Expired due to Fees

• Current Assignee: Ostendo Technologies Inc.
• Original Assignee: Ostendo Technologies Inc.
• Inventors: El-Ghoroury, Hussein S., Chuang, Chih-Li, Yadavalli, Kameshwar, Fan, Qian
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US13/463,130
• Publication Number:
  US 20120288995A1
• Time in Patent Office: 957 Days
• Field of Search: 438/119, 438/23, 438/25, 257/E21.514, 349/45, 385/30, 385/51, 385/91
• US Class Current: 438/24
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0066 with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Abstract

Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.

Claims

1. A method for the bonding of a III-V semiconductor wafer to a CMOS silicon wafer comprising:

forming bonding surfaces on the wafers for the transfer of electric signals between the bonded wafers by;

forming a dielectric intermediary bonding layer on a surface of each wafer, within which surface is embedded electrical interconnects for the transfer of electrical signals;

respectively;

planarizing the surfaces of the dielectric intermediary bonding layers of the two wafers;

interfusing the electrical interconnects and the dielectric intermediary bonding layer on the wafers to bond the wafers together with electrical interconnections between the wafers;

wherein the density of the electrical interconnects across the bonding interface is more than one million electrical interconnects per square centimeter;

wherein the III-V semiconductor wafer is a photonic wafer comprising multiple III-V material layers deposited on an epitaxial growth substrate and cross etched to delineate an array comprising a multiplicity of photonic elements, and further cross etched to delineate the die boundaries of the array.

2. The method of claim 1 wherein the cross etching is done prior to the interfusion.

3. The method of claim 1 wherein each photonic element has a size of 10×

10 microns or less.

4. The method of claim 1 wherein the density of the electrical interconnects across the bonding interface is 4 million electrical interconnects per square centimeter or higher.

5. The method of claim 1 wherein the III-V semiconductor wafer is formed in at least one epitaxial layer on an epitaxial growth substrate bonded to act as a host wafer.

6. The method of claim 5 wherein the epitaxial growth substrate is removed after the interfusion using a laser lift-off process, an epitaxial lift-off process or a chemical mechanical polishing lift-off process.

7. The method of claim 1 wherein the III-V material epitaxial layers of the photonic wafer are cross etched in two orthogonal directions through the photonic wafer to form trenches all the way to its epitaxial growth substrate.

8. The method of claim 7 wherein the trenches are refilled with metallic materials or dielectric materials.

9. The method of claim 1 wherein the dielectric intermediary bonding layers are selected to have a coefficient of thermal expansion between the coefficients of thermal expansion of the two wafers.

10. The method of claim 9 wherein the thickness of the dielectric intermediary bonding layers is substantially equal to the height of the electrical interconnects above the surface of the wafers.

11. The method of claim 9 wherein the planarization is controlled to provide a surface of the electrical interconnects slightly below the planarized surfaces of the dielectric intermediary bonding layers.