Bypass for on-chip voltage regulator

• US 8,917,118 B2
• Filed: 10/25/2012
• Issued: 12/23/2014
• Est. Priority Date: 07/25/2012
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Knoedgen, Horst
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/660,165
• Publication Number:
  US 20140028356A1
• Time in Patent Office: 789 Days
• US Class Current: 327/108
• CPC Class Codes: H02M 1/0006 Arrangements for supplying an adequate voltage to the control circuit of converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/327 against abnormal temperatures
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 19/0019 by energy recovery or adiabatic operation
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present document relates to a reduction of heat generated in driver circuits comprising voltage regulators. A circuit arrangement comprises a driver circuit configured to generate a control signal for driving a power switch. The driver circuit comprises a voltage regulator configured to generate a second voltage from a supply voltage, a drive unit configured to generate the control signal based on the supply voltage and configured to provide the control signal to a control interface of the driver circuit, and a logic component operating at the second voltage and drawing a second current, and configured to control the drive unit. Furthermore, the circuit arrangement comprises bypass circuitry coupled at an input to the control interface and configured to provide at an output at least part of the second current to the logic component.

Claims

1. A circuit arrangement comprising

a driver circuit configured to generate a control signal at a high voltage and at a low voltage for driving a power switch;

wherein the driver circuit comprises

a voltage regulator configured to generate a second voltage from a supply voltage;

a drive unit configured to generate the control signal based on the supply voltage and configured to provide the control signal to a control interface of the driver circuit; and

a logic component operating at the second voltage and drawing a second current, and configured to control the drive unit; and

a bypass circuitry coupled at an input to the control interface and configured to provide at an output at least part of the second current to the logic component, when the control signal is at high voltage;

wherein

the driver circuit comprises a plurality of drive units configured to generate a plurality of control signals for a plurality of power switches, respectively, and configured to provide the plurality of control signals to a plurality of control interfaces of the driver circuit, respectively; and

the circuit arrangement comprises a plurality of bypass circuitries, each coupled at an input to a respective control interface and each configured to provide at an output at least part of the second current to the logic component.

2. The circuit arrangement of claim 1, wherein

the circuit arrangement further comprises a capacitor interface coupled to an output of the voltage regulator providing the second voltage;

the output of the bypass circuitry is coupled to the capacitor interface.

3. The circuit arrangement of claim 2, wherein the circuit arrangement further comprises a stabilizing capacitor coupled to the capacitor interface.

4. The circuit arrangement of claim 2, wherein the logic component is coupled to the capacitor interface.

5. The circuit arrangement of claim 1, wherein the control signal comprises

a high voltage signal at the supply voltage;

and/or

a low voltage signal at ground.

6. The circuit arrangement of claim 1, wherein the bypass circuitry comprises

a bypass resistor;

and/or

a bypass diode configured to block a current from the output of the bypass circuitry to the input of the bypass circuitry.

7. The circuit arrangement of claim 1, wherein

at least some of the plurality of control signals are alternating between a high voltage and a low voltage;

the plurality of control signals are such that when at least one of the plurality of control signals is at high voltage, at least another of the plurality of control signals is at low voltage; and

the plurality of bypass circuitries are designed such that a sum of the currents provided at the outputs of the plurality of bypass circuitries is substantially constant.

8. The circuit arrangement of claim 1, wherein

the driver circuit is part of an integrated circuit;

and/or

the bypass circuitry is external to the integrated circuit; and

/or

the power switch is external to the integrated circuit.

9. The circuit arrangement of claim 8, wherein the circuit is an integrated circuit using CMOS technology.

10. The circuit arrangement of claim 1, wherein

the voltage regulator is a linear regulator;

and/or

the voltage regulator comprises a transistor operated in its linear region.

11. The circuit arrangement of claim 1, wherein

the supply voltage is in the range of 12 to 15V;

and/or

the second voltage is in the range of 1-5V.

12. The circuit arrangement of claim 1, wherein the driver circuit further comprises a supply interface configured to receive the supply voltage from a power supply external to the driver circuit.

13. The circuit arrangement of claim 1, wherein the voltage regulator is configured to sink current provided at the output of the bypass circuitry, which exceeds the second current.

14. The circuit arrangement of claim 1, wherein the circuit arrangement is configured to generate one or more control signals.

15. The circuit arrangement of claim 14, wherein one or more power switches are controlled using the respective one or more control signals, wherein the one or more power switches form a half-bridge or a full-bridge.

16. The circuit arrangement of claim 15, wherein the one or more power switches are field effect transistors.

17. A method to reduce heat generated within a driver circuit used to drive an external power switch, the method comprising

providing a driver circuit comprising a voltage regulator, a drive unit, and logic components configured to control the drive unit, an external power switch driven by the driver circuit, a supply voltage, and a bypass circuitry;

generating by the driver circuit a control signal at a high voltage and at a low voltage for driving the power switch;

implementing the bypass circuitry comprising a resistor, wherein the bypass circuitry is external to the driver circuit;

splitting power losses between the voltage regulator and the bypass resistor, by providing current to the logic components using the bypass circuitry, when the control signal is at high voltage, wherein a sum of the power losses remains unchanged by the splitting; and

generating a plurality of control signals respectively for a plurality of power switches via a plurality of control interfaces by a plurality of drive units, wherein a plurality of bypass circuitries, each coupled at an input to a respective control interface, and each provides at an output at least part of a second current to the logic component.

18. The method of claim 17 wherein the drive unit generates the control signal based on the supply voltage and provides the control signal to a control interface of the driver circuit.

19. The method of claim 18 further comprises generating a second voltage from the supply voltage by the voltage generator.

20. The method of claim 19 further comprises controlling the drive unit by the logic component, wherein the logic components is operating at the second voltage and is drawing a second current.

21. The method of claim 20, further comprises providing at least a part of the second current to the logic component by the bypass circuitry via a control interface.

22. The method of claim 21 further comprises providing the second voltage via a capacitor interface coupled to an output of the voltage regulator output voltage wherein the output of the bypass circuitry is coupled to the capacitor interface.

23. The method of claim 17, wherein the control signal comprises a high voltage signal at the supply voltage and/or a low voltage signal at ground.

24. The method of claim 17 further comprises blocking a current from an output of the bypass circuitry to an input of the bypass circuitry by a diode.

25. The method of claim 17, wherein at least some of the plurality of control signals are alternating between a high voltage and a low voltage and wherein the plurality of control signals are such that when at least one of the plurality of control signals is at high voltage, at least another of the plurality of control signals is at low voltage, and the plurality of bypass circuitries are designed such that a sum of the currents provided at the outputs of the plurality of bypass circuitries is substantially constant.

26. The method of claim 17, wherein the driver circuit is part of an integrated circuit and the bypass circuitry and the power switch are external to the integrated circuit.