Apparatus and method for checking an error detection functionality of a data processor

• US 8,918,679 B2
• Filed: 01/12/2007
• Issued: 12/23/2014
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Janke, Marcus, Laackmann, Peter
• Primary Examiner(s): SCHELL, JOSEPH O
• Application Number:
  US11/622,775
• Publication Number:
  US 20070277070A1
• Time in Patent Office: 2,902 Days
• Field of Search: 714/41, 714/23, 714/25
• US Class Current: 714/41
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards

Abstract

An apparatus for checking an error detection functionality of a data processing circuit, comprising an arithmetic logic unit, which provides an output datum based on an input datum, and an error detection circuit that executes the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and generates an error signal, if an error is present, which comprises a control circuit that passes the error signal through to an error signal output in a normal operating mode, and blocks the error signal in a checking mode, does not let the error signal pass to the error signal output, influences the arithmetic logic unit, the error detection circuit or the input datum such that the error detection circuit detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, outputs an alarm signal indicating an incorrect execution of the error detection functionality.

Claims

1. A chip card or smart card security controller comprising

a data processor having an arithmetic logic unit configured to calculate an output datum based on at least one an input datum,

an error detector configured to check the output datum for an error based on the output datum and the at least one input datum, and, if an error is present, generates an error signal;

and

a controller configured to

alternately switch between a normal operating mode and a checking mode,

pass the error signal through to an error signal output in the normal operating mode, and blocks the error signal in a checking mode, in order to not let the error signal pass through to the error signal output;

each time the controller switches to the checking mode,

influences the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error and, if no error signal is received in response to the influencing, output an alarm signal indicating an incorrect execution of the error detection functionality; and

subsequently, cause the error detector to check the output datum with regard to an error without influencing the arithmetic logic unit, the error detector and the input datum, and output the alarm signal, if the controller receives a further error signal from the error detector in response to the causing,

a circuit adapted to execute a security reset in response to receiving the alarm signal, and adapted to perform one of a termination of a program currently running on the chip card, a security reset and a renewal of an instruction initiating the calculation of the arithmetic logic unit, in response to receiving the error signal via the error signal output.

2. The chip card or smart card security controller according to claim 1, wherein the data processor comprises a further arithmetic logic unit configured to compute a further output datum based on a further at least one input datum so that, in case of the further at least one input datum being equal to the at least one input datum, the further output datum equals the output datum, and wherein the error detector is configured to check the output datum on the basis of a comparison between the output datum and the further output datum.

3. The chip card or smart card security controller according to claim 2, wherein the controller is configured to, in the influencing concurrently and in a manner different from the arithmetic logic unit, influence the further arithmetic logic unit or the further input datum, to cause an error during correct execution of the error detection functionality by the error detector.

4. The chip card or smart card security controller according to claim 2, wherein the chip card is configured such that, preliminarily, the error detector is disabled and the further arithmetic logic unit is used along with the arithmetic logic unit separately and concurrently for different calculations so as to accelerate a calculation task.

5. The chip card or smart card security controller according to claim 1, wherein the error detector infers an error when the output datum fulfills a predetermined condition.

6. The chip card or smart card security controller according to claim 1, wherein the error detector infers an error when the output datum and the input datum do not have a predetermined relation to each other.

7. The chip card or smart card security controller according to claim 1, wherein the controller is configured to switch to the checking mode each time a predetermined trigger condition is fulfilled, and switch back to the normal operating mode upon the influencing and subsequent causing.

8. The chip card or smart card security controller according to claim 7, wherein the controller is configured such that the predetermined trigger condition is fulfilled on a regularly basis, in case of an arrival of a predetermined CPU instruction, or on a random basis.

9. A digital memory medium comprising a program with program code for performing the method comprising:

calculating, performed by an arithmetic logic unit, an output datum based on at least one an input datum,

checking, performed by an error detector, the output datum for an error based on the output datum and the at least one input datum, and, if an error is present, generate an error signal, and

alternately switching between a normal operating mode and a checking mode,

passing the error signal through to an error signal output in the normal operating mode, and blocking the error signal in a checking mode, in order to not let the error signal pass through to the error signal output;

each time the checking mode is switched to,

influencing the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error and, if no error signal is received in response to the influencing, outputting an alarm signal indicating an incorrect execution of the error detection functionality; and

subsequently, causing the error detector to check the output datum with regard to an error without influencing the arithmetic logic unit, the error detector and the input datum, and outputting the alarm signal, if the controller receives a further error signal from the error detector in response to the causing,

executing a security reset in response to receiving the alarm signal, and

performing one of a termination of a program currently running on the chip card, a security reset and a renewal of an instruction initiating the calculation of the arithmetic logic unit, in response to receiving the error signal via the error signal output.

10. A method, comprising:

calculating, performed by an arithmetic logic unit, an output datum based on at least one an input datum,

checking, performed by an error detector, the output datum for an error based on the output datum and the at least one input datum, and, if an error is present, generate an error signal, and

alternately switching between a normal operating mode and a checking mode,

passing the error signal through to an error signal output in the normal operating mode, and blocking the error signal in a checking mode, in order to not let the error signal pass through to the error signal output;

each time the checking mode is switched to,

influencing the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error and, if no error signal is received in response to the influencing, outputting an alarm signal indicating an incorrect execution of the error detection functionality; and

subsequently, causing the error detector to check the output datum with regard to an error without influencing the arithmetic logic unit, the error detector and the input datum, and outputting the alarm signal, if the controller receives a further error signal from the error detector in response to the causing,

executing a security reset in response to receiving the alarm signal, and

performing one of a termination of a program currently running on the chip card, a security reset and a renewal of an instruction initiating the calculation of the arithmetic logic unit, in response to receiving the error signal via the error signal output.