Three-dimensional semiconductor memory device with active patterns and electrodes arranged above a substrate

• US 8,923,057 B2
• Filed: 12/30/2010
• Issued: 12/30/2014
• Est. Priority Date: 02/18/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Yong-Hoon, Lee, Myoung Bum, Hwang, Ki Hyun, Baik, Seung Jae
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US12/981,625
• Publication Number:
  US 20110199804A1
• Time in Patent Office: 1,461 Days
• Field of Search: 365/51, 365/72, 365/63, 365/185.17, 365/185.05, 257/329, 257/210, 257/211, 257/208, 257/686
• US Class Current: 365/185.17
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Claims

1. A three-dimensional semiconductor device, comprising:

an electrode structure comprising a plurality of electrodes disposed at a plurality of levels one above the other in the device such that the electrode structure is three-dimensional;

a plurality of active patterns each extending vertically through the electrode structure,

wherein respective ones of the electrodes are disposed on opposite sides of each of the active patterns; and

information storage elements disposed between the electrodes of the electrode structure and the plurality of active patterns,

wherein one of the electrodes disposed on one of the opposite sides of each of the active patterns is electrically isolated in the device from one of the electrodes disposed on the other of the opposite sides of the active pattern.

2. The three-dimensional semiconductor device of claim 1, wherein the electrode structure comprises first through m-th electrode groups each comprising a plurality of vertically stacked electrodes, the first through m-th electrode groups being arranged horizontally from the first electrode group to the m-th electrode group, where m is a natural number,

wherein the active patterns are disposed between a (2n+1)-th electrode group and a (2n+2)-th electrode group, where n is a natural number, and

at least one of the electrodes in the (2n+1)-th electrode group is electrically separated from all of the electrodes in the (2n+2)-th electrode group.

3. The three-dimensional semiconductor device of claim 2, wherein the three-dimensional semiconductor device comprises a first connection region, a second connection region, and a cell array region between the first connection region and the second connection region,

wherein electrodes in the (2n+1)-th electrode group and electrodes in a (2n+3)-th electrode group that are positioned at the same height are connected in the first connection region and are in an equipotential state, and

wherein electrodes in the (2n+2)-th electrode group and electrodes in a (2n+4)-th electrode group that are positioned at the same height are connected in the second connection region and are in an equipotential state.

4. The three-dimensional semiconductor device of claim 2, wherein the three-dimensional semiconductor device comprises a first connection region, a second connection region, and a cell array region between the first connection region and the second connection region,

wherein electrodes in the (2n+2)-th electrode group and electrodes in a (2n+3)-th electrode group that are positioned at the same height are connected to each other in the first connection region and are in an equipotential state, and

wherein electrodes in a (2n+4)-th electrode group and electrodes in a (2n+5)-th electrode group that are positioned at the same height are connected to each other in the second connection region and are in an equipotential state.

5. The three-dimensional semiconductor device of claim 2, wherein the three-dimensional semiconductor device comprises a first connection region, a second connection region, and a cell array region between the first connection region and the second connection region, and further comprises:

first interconnection lines connected to electrodes in the first connection region; and

second interconnection lines connected to electrodes in the second connection region.

6. The three-dimensional semiconductor device of claim 5, wherein each of the first interconnection lines electrically connects electrodes in the (2n+1)-th electrode group and a (2n+3)-th electrode group that are positioned at the same height, and each of the second interconnection lines electrically connects electrodes in the (2n+2)-th electrode group and a (2n+4)-th electrode group that are positioned at the same height.

7. The three-dimensional semiconductor device of claim 5, wherein each of the first interconnection lines electrically connects electrodes in the (2n+2)-th electrode group and a (2n+3)-th electrode group that are positioned at the same height, and each of the second interconnection lines electrically connects electrodes in a (2n+4)-th electrode group and a (2n+5)-th electrode group that are positioned at the same height.

8. The three-dimensional semiconductor device of claim 5, further comprising bit lines that are connected to the active patterns and cross the electrodes in the cell array region, wherein the first and second interconnection lines have substantially the same material, height, or thickness as the bit lines.

9. The three-dimensional semiconductor device of claim 1, further comprising:

a substrate disposed below the electrode structure; and

source lines disposed below the electrode structure,

wherein the source lines comprise a semiconductor material having a different conductivity type compared to the substrate and the active patterns.

10. The three-dimensional semiconductor device of claim 9, wherein the electrode structure comprises first through m-th electrode groups each comprising a plurality of vertically stacked electrodes, the first through m-th electrode groups being arranged horizontally from the first electrode group to the m-th electrode group, where m is a natural number, and

wherein the source lines comprise an impurity region formed in the substrate between a (2n+2)-th electrode group and a (2n+3)-th electrode group, where n is a natural number.

11. The three-dimensional semiconductor device of claim 1, further comprising:

semiconductor pads disposed on the active patterns; and

bit lines crossing the electrodes and electrically connected to the semiconductor pads,

wherein the semiconductor pads are formed of a semiconductor material having a different conductivity type from at least one portion of the active pattern.

12. The three-dimensional semiconductor device of claim 1, wherein each of the active patterns comprises a first region and a second region that are spaced apart from each other, and wherein the first and second regions are formed facing respective sidewalls of two adjacent electrode groups.

13. The three-dimensional semiconductor device of claim 12, wherein each of the active patterns further comprises a connection part connecting lower portions of the first and second regions.

14. The three-dimensional semiconductor device of claim 1, further comprising a substrate disposed below the electrode structure, wherein bottom surfaces of the active patterns are lower than a top surface of the substrate.

15. A three-dimensional semiconductor device, comprising:

a two-dimensional array of active patterns arranged on a substrate;

electrodes interposed between the active patterns, and wherein a plurality of the electrodes are disposed at each of a plurality of levels one above the other on the substrate such that the electrodes constitute a structure that is three-dimensional; and

memory regions located at points where the active patterns are closest to the electrodes, respectively,

wherein each of the active patterns provides a common path for current to two of the memory regions disposed at the same level as one another above the substrate.

16. The three-dimensional semiconductor device of claim 15, wherein one of the electrodes disposed on one of the opposite sides of each of the active patterns and another of the electrodes disposed on the other of the opposite sides of the active pattern at the same level above the substrate as said one of the electrodes are electrically isolated from each other in the device.

17. The three-dimensional semiconductor device of claim 16, wherein each of the active patterns comprises a first region and a second region spaced apart from each other, and the first and second regions are formed facing sidewalls of the two electrically isolated electrodes.