Semiconductor device and method for fabricating the same

• US 8,933,509 B2
• Filed: 02/08/2011
• Issued: 01/13/2015
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Choi, Shin Gyu, Oh, Seung Chul
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US13/023,427
• Publication Number:
  US 20110121388A1
• Time in Patent Office: 1,435 Days
• Field of Search: 257/334, 257/332, 257/E29.257
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.

Claims

1. A semiconductor device comprising:

a device isolation structure formed in a semiconductor substrate, the device isolation structure defining an active region;

a recess channel structure disposed in the semiconductor substrate under the active region;

a first lower gate conductive layer on the surface of the recess channel structure and defining a recess;

a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, the holding layer configured to hold a shift of a seam occurring in the recess channel structure;

a second lower gate conductive layer over and directly contacting the first lower gate conductive layer and the holding layer wherein the holding layer is surrounded by the first and the second lower gate conductive layers; and

an upper gate conductive layer over the second lower gate conductive layer.

2. The semiconductor device according to claim 1, wherein the recess channel structure includes an upper recess channel structure and a lower recess channel structure, the lower recess channel structure having a latitudinal width greater than that of the upper recess channel structure.

3. The semiconductor device according to claim 1, wherein the first lower gate conductive layer includes a polysilicon layer doped with impurity ions.

4. The semiconductor device according to claim 3, wherein the polysilicon layer doped with impurity ions is amorphous.

5. The semiconductor device according to claim 4, wherein the impurity ions include phosphorous (P) with a concentration in the range of about 1.0E20 ions/cm³ to about 4.0E20 ions/cm³.

6. The semiconductor device according to claim 1, wherein the second lower gate conductive layer includes a polysilicon layer doped with impurity ions.

7. The semiconductor device according to claim 6, wherein the impurity ions include boron (B) or phosphorous (P) with a concentration in the range of about 1.0E15 ions/cm³ to about 7.0E15 ions/cm³.

8. The semiconductor device according to claim 7, wherein the second lower gate conductive layer in a PMOS region is formed of the polysilicon layer doped with boron (B).

9. The semiconductor device according to claim 7, wherein the second lower gate conductive layer in a NMOS region is formed of the polysilicon layer doped with phosphorous (P).

10. The semiconductor device according to claim 1, wherein the holding layer is selected from the group consisting of an insulating film, a metal film, a conductive layer, and combinations thereof.

11. The semiconductor device according to claim 10, wherein the holding layer is an oxide film or a crystalline polysilicon layer.

12. The semiconductor device according to claim 1, further comprising a gate insulating film disposed at the interface between the gate electrode and the semiconductor substrate including the recess channel structure.

13. The semiconductor device according to claim 1, further comprising a gate hard mask layer pattern disposed over the second lower gate conductive layer.

14. The semiconductor device according to claim 1, wherein the holding layer is configured to expose at least a portion of the first lower gate conductive layer to allow the second lower gate conductive layer to directly contact the first lower gate conductive layer.

15. The semiconductor device according to claim 1, wherein the holding layer comprises an insulating film.

16. A semiconductor device comprising:

a device isolation structure formed in a semiconductor substrate having a PMOS region and a NMOS region, the device isolation structure defining an active region;

a bulb-type recess channel structure disposed in the semiconductor substrate under the active region;

a lower gate electrode disposed over the active region, the lower gate electrode including a stacked structure having a first lower gate conductive layer, a holding layer, and a second lower gate conductive layer to fill the bulb-type recess channel structure, wherein the first lower gate conductive layer is formed of a polysilicon layer doped with impurity ions, the holding layer is configured to hold a shift of a seam occurring in the recess channel structure, and the second lower gate conductive layer is formed of a polysilicon layer doped with impurity ions wherein the impurity ions in the PMOS region and the NMOS region are different, wherein the second lower gate conductive layer being disposed over and directly contacting the first lower gate conductive layer and the holding layer; and

an upper gate conductive layer over the second lower gate conductive layer.

17. The semiconductor device according to claim 16, wherein a portion of the second lower gate conductive layer is disposed in a bottom portion of the bulb-type recess.