Methods of forming finfet devices with a shared gate structure

• US 8,936,986 B2
• Filed: 03/12/2013
• Issued: 01/20/2015
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wei, Andy C., Yang, Dae Geun
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US13/797,117
• Publication Number:
  US 20140273429A1
• Time in Patent Office: 679 Days
• Field of Search: 438/157, 438/176, 438/283, 257/E21.623, 257/E21.637
• US Class Current: 438/283
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Claims

1. A method, comprising:

forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, said second type being opposite to said first type; and

forming a first sidewall spacer around an entire perimeter of said shared sacrificial gate structure in a single deposition process operation and a single etching process operation.

2. The method of claim 1, further comprising forming a sacrificial layer of insulating material above said shared sacrificial gate structure, on said first sidewall spacer, on said at least one first fin and on said at least one second fin.

3. The method of claim 2, further comprising:

forming a first etch mask above said first type of FinFET device and performing an etching process on said sacrificial layer of insulating material to define a second sidewall spacer positioned on a first portion of said first sidewall spacer;

removing said first etch mask; and

forming a second etch mask above said second type of FinFET device and performing an etching process on said sacrificial layer of insulating material to define a third sidewall spacer positioned on a second portion of said first sidewall spacer.

4. The method of claim 1, wherein said first type of FinFET device is an N-type FinFET device and said second type of FinFET device is a P-type FinFET device.

5. The method of claim 1, wherein said first type of FinFET device is a P-type FinFET device and said second type of FinFET device is an N-type FinFET device.

6. The method of claim 1, wherein said sacrificial gate structure is comprised of a layer of silicon dioxide and a layer of polysilicon positioned above said layer of silicon dioxide.

7. The method of claim 1, wherein said first sidewall spacer is comprised of silicon nitride, silicon oxynitride or silicon nitride carbon, and said sacrificial layer of insulating material is comprised of silicon dioxide.

8. The method of claim 1, wherein said step of forming said first sidewall spacer in the single deposition process operation and the single etching process operation comprises performing a multi-step etching sequence comprised of a main etch period and an over-etch period.

9. A method, comprising:

forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, said second type being opposite to said first type;

forming a first sidewall spacer comprised of silicon nitride around an entire perimeter of said shared sacrificial gate structure in a single deposition process operation and a single etching process operation;

forming a sacrificial layer comprised of silicon dioxide above said shared sacrificial gate structure, on said first sidewall spacer, on said at least one first fin and on said at least one second fin;

forming a first etch mask above said first type of FinFET device and performing an etching process on said sacrificial layer to define a second sidewall spacer comprised of silicon dioxide positioned on a first portion of said first sidewall spacer;

removing said first etch mask; and

forming a second etch mask above said second type of FinFET device and performing an etching process on said sacrificial layer to define a third sidewall spacer comprised of silicon dioxide positioned on a second portion of said first sidewall spacer.

10. The method of claim 9, further comprising performing an etching process to remove said second and third sidewall spacers.

11. The method of claim 10, further comprising performing an epitaxial deposition process to form a semiconducting material on said at least one second fin.

12. A method, comprising:

forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, said second type being opposite to said first type;

forming a first sidewall spacer around an entire perimeter of said shared sacrificial gate structure in a single deposition process operation and a single etching process operation;

forming a sacrificial layer of insulating material above said shared sacrificial gate structure, on said first sidewall spacer, on said at least one first fin and on said at least one second fin;

forming a first etch mask that covers said first type of FinFET device and exposes said second type of FinFET device including said at least one second fin;

performing an etching process through said first etch mask on said sacrificial layer of insulating material to define a second sidewall spacer positioned on a first portion of said first sidewall spacer;

performing an etching process to remove a portion of said at least one second fin such that said at least one second fin has a recessed surface that is positioned below an upper surface of an adjacent isolation region; and

performing an epi deposition process to form a semiconductor material on said recessed surface of said at least one second fin.

13. The method of claim 12, wherein said first type of FinFET device is an N-type FinFET device and said second type of FinFET device is a P-type FinFET device.

14. The method of claim 12, wherein said first type of FinFET device is a P-type FinFET device and said second type of FinFET device is an N-type FinFET device.

15. The method of claim 12, wherein said shared sacrificial gate structure is comprised of a layer of silicon dioxide and a layer of polysilicon positioned above said layer of silicon dioxide.

16. The method of claim 12, wherein said first sidewall spacer is comprised of silicon nitride, silicon oxynitride or silicon nitride carbon, and said sacrificial layer of insulating material is comprised of silicon dioxide.

17. The method of claim 12, wherein said step of forming said first sidewall spacer in the single deposition process operation and the single etching process operation comprises performing a multi-step etching sequence comprised of a main etch period and an over-etch period.