Frequency scaling of variable speed systems for fast response and power reduction

• US 8,937,511 B2
• Filed: 11/20/2012
• Issued: 01/20/2015
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas, Sutardja, Sehat
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US13/681,737
• Publication Number:
  US 20130127550A1
• Time in Patent Office: 791 Days
• Field of Search: 331/57
• US Class Current: 331/57
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 3/02 Generators characterised by the type of circuit or by the means used for producing pulses H03K3/64 - H03K3/84 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.

Claims

1. A system comprising:

a plurality of amplifiers configured to

generate a clock signal having a frequency,

wherein the clock signal is input to a processor,

wherein the amplifiers are connected in series,

wherein an output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers, and

wherein each of the amplifiers has a transconductance; and

a frequency adjustment module configured to adjust, based on an activity level of the processor, the frequency of the clock signal by (i) initially adjusting a supply voltage of the plurality of amplifiers until the supply voltage reaches a minimum or maximum value of a predetermined range, and (ii) subsequent to the supply voltage of the plurality of amplifiers reaching the minimum or maximum value of the predetermined range, adjusting the transconductance of the amplifiers.

2. The system of claim 1, wherein:

the amplifiers include inverters, and

the inverters are configured to operate as a ring oscillator.

3. The system of claim 1, further comprising an activity monitoring module configured to determine the activity level of the processor by counting a number of wait-for-interrupt states of the processor within a predetermined time period.

4. The system of claim 3, wherein the frequency adjustment module is configured to:

compare the number of wait-for-interrupt states to a first threshold and a second threshold, wherein the second threshold is greater than the first threshold,

increase the frequency of the clock signal in response to the number of wait-for-interrupt states being less than or equal to the first threshold, and

decrease the frequency of the clock signal in response to the number of wait-for-interrupt states being greater than or equal to the second threshold.

5. The system of claim 1, wherein each of the amplifiers includes an input configured to receive a control signal to adjust the transconductance of the amplifiers, the system further comprising a digital-to-analog converter configured to:

receive data based on the activity level of the processor, and

generate, based on the data, the control signal to adjust the transconductance of the amplifiers.

6. The system of claim 1, further comprising:

a plurality of capacitances and a plurality of switches connected respectively across an output of each of the amplifiers and a common potential, wherein a total capacitance across the output of each of the amplifiers depends on states of the plurality of switches; and

a capacitor switching module configured to adjust, based on the activity level of the processor, the transconductance of the amplifiers by controlling the states of the switches.

7. The system of claim 6, wherein:

the frequency adjustment module is configured to adjust the transconductance of the amplifiers by adjusting the supply voltage of the plurality of amplifiers until the supply voltage reaches a predetermined value, and

the capacitor switching module is configured to adjust the transconductance of the amplifiers after the supply voltage reaches the predetermined value.

8. A system comprising:

a plurality of amplifiers configured to

generate a clock signal having a frequency,

wherein the clock signal is input to a processor,

wherein the amplifiers are connected in series,

wherein an output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers, and

wherein each of the amplifiers has a transconductance;

a frequency adjustment module configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers, wherein the transconductance of the amplifiers is adjusted by adjusting a supply voltage of the plurality of amplifiers within a predetermined range; and

a numerically controlled oscillator configured to

generate a signal, and

receive, based on the activity level of the processor within a predetermined time period, a plurality of inputs during a plurality of portions of the predetermined time period,

wherein the inputs adjust a frequency of the signal; and

a gating module configured to

receive the signal generated by the numerically controlled oscillator, and

output the clock signal to the processor in accordance with the signal generated by the numerically controlled oscillator.

9. The system of claim 8, wherein:

the frequency adjustment module is configured to adjust the transconductance of the amplifiers by adjusting the supply voltage of the plurality of amplifiers until the supply voltage reaches a predetermined value, and

the numerically controlled oscillator is configured to generate the signal after the supply voltage reaches the predetermined value.

10. A system comprising:

a plurality of amplifiers configured to

generate a clock signal having a frequency,

wherein the clock signal is input to a processor,

wherein the amplifiers are connected in series,

wherein an output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers,

wherein each of the amplifiers has a transconductance, and

wherein each of the amplifiers includes an input configured to receive a control signal to adjust the transconductance;

a frequency adjustment module configured to

adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers,

wherein the transconductance of the amplifiers is adjusted by adjusting a supply voltage of the plurality of amplifiers until the supply voltage reaches a predetermined value within a predetermined range; and

a digital-to-analog converter configured to

receive data based on the activity level of the processor,

generate, based on the data, the control signal to adjust the transconductance of the amplifiers, and

adjust the transconductance of the amplifiers after the supply voltage reaches the predetermined value.

11. A system comprising:

a ring oscillator including a plurality of inverters configured to

generate a clock signal having a frequency,

wherein the clock signal is supplied to a processor, and

wherein each of the inverters has a transconductance; and

a frequency adjustment module configured to

receive an activity level of the processor, and

adjust, based on the activity level of the processor, the frequency of the clock signal by (i) initially adjusting a supply voltage of the plurality of inverters until the supply voltage reaches a minimum or maximum value of a predetermined range, and (ii) subsequent to the supply voltage of the plurality of inverters reaching the minimum or maximum value of the predetermined range, adjusting the transconductance of the inverters.

12. The system of claim 11, wherein each of the inverters includes an input configured to receive a control signal to adjust the transconductance of the inverters, the system further comprising a digital-to-analog converter configured to:

receive data based on the activity level of the processor, and

generate, based on the data, the control signal to adjust the transconductance of the inverters.

13. The system of claim 11, further comprising:

a plurality of capacitances and a plurality of switches connected respectively across an output of each of the inverters and a common potential, wherein a total capacitance across the output of each of the inverters depends on states of the plurality of switches; and

a capacitor switching module configured to adjust, based on the activity level of the processor, the transconductance of the inverters by controlling the states of the switches.

14. A system comprising:

a ring oscillator including a plurality of inverters configured to

generate a clock signal having a frequency,

wherein the clock signal is supplied to a processor, and

wherein each of the inverters has a transconductance;

a frequency adjustment module configured to

receive an activity level of the processor, and

adjust, based on the activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the inverters,

wherein the transconductance of the inverters is adjusted by adjusting a supply voltage of the plurality of inverters within a predetermined range; and

a numerically controlled oscillator configured to

generate a signal, and

receive, based on the activity level of the processor within a predetermined time period, a plurality of inputs during a plurality of portions of the predetermined time period,

wherein the inputs adjust a frequency of the signal; and

a gating module configured to

receive the signal generated by the numerically controlled oscillator, and

output the clock signal to the processor in accordance with the signal generated by the numerically controlled oscillator.

15. A method comprising:

generating a clock signal for a processor using a plurality of inverters connected in series, wherein the clock signal has a frequency, and wherein each of the inverters has a transconductance;

receiving an activity level of the processor; and

adjusting, based on the activity level of the processor, the frequency of the clock signal by (i) initially adjusting a supply voltage of the plurality of inverters until the supply voltage reaches a minimum or maximum value of a predetermined range, and (ii) subsequent to the supply voltage of the plurality of inverters reaching the minimum or maximum value of the predetermined range, adjusting the transconductance of the inverters.

16. The method of claim 15, further comprising:

converting data indicating the activity level of the processor to a control signal; and

adjusting the transconductance of the inverters by supplying the control signal to an input of each of the inverters,

wherein the input of each of the inverters is configured to receive the control signal to adjust the transconductance of the respective inverter.

17. The method of claim 15, further comprising:

connecting a plurality of capacitances and a plurality of switches respectively across an output of each of the inverters and a common potential, wherein a total capacitance across the output of each of the inverters depends on states of the plurality of switches; and

adjusting, based on the activity level of the processor, the transconductance of the inverters by controlling the states of the switches.

18. A method comprising:

generating a clock signal for a processor using a plurality of inverters connected in series, wherein the clock signal has a frequency, and wherein each of the inverters has a transconductance;

receiving an activity level of the processor;

adjusting, based on the activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the inverters, wherein the transconductance of the inverters is adjusted by adjusting a supply voltage of the plurality of inverters within a predetermined range;

generating a signal using a numerically controlled oscillator;

receiving, based on the activity level of the processor within a predetermined time period, a plurality of inputs during a plurality of portions of the predetermined time period, wherein the inputs adjust a frequency of the signal; and

outputting the clock signal to the processor in accordance with the signal generated by the numerically controlled oscillator.