High-power induction-type power supply system and its bi-phase decoding method
First Claim
1. A bi-phase data signal decoding method used in a high-power induction-type power supply system consisting of a supplying-end module and a receiving-end module for decoding a data code of a data signal, comprising steps of:
- (a) set a built-in forward phase comparator and a built-in reverse phase comparator of a supplying-end microprocessor of the supplying-end module to initialize interruption data analysis and to clear register data;
(b) wait for an interruption triggering;
(c) determine whether or not the interruption triggered, and then proceed to step (e) when positive or step (d) when negative;
(d) determine whether or not a maximum data length counter is overflow, and then return to step (a) when positive or step (b) when negative;
(e) judge a phase to be a forward phase or a reverse phase, and then proceed to step (f) when the forward phase is judged, or step (g) when the reverse phase is judged;
(f) a first trigger is judged to be a forward phase, thus, set to turn off reverse phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (f) to be a forward phase triggering until that a new setting is made, and then proceed to step (h);
(g) the first trigger is judged to be a reverse phase, thus set to turn off forward phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (g) to be a reverse phase triggering until that a new setting is made, and then proceed to step (h);
(h) check a signal length to be in match with a set length or not, and then proceed to step (i) when positive or step (j) when negative;
(i) the signal length is checked in match with the set length, thus, set bit data and then proceed to step (k);
(j) the signal length is checked not in match with the set length, thus, a signal is determined to be a noise, and then clear existing data and re-set to return to step (a);
(k) check whether or not a set number of bits has been received, and then proceed to step (l) when negative or step (m) when positive;
(l) receiving of the set number of bits is not completed, thus, wait for a next interruption triggering and then return to step (c);
(m) the set number of bits has been completely received, thus, set data into a data register, and then initialize a built-in data analysis program and then run step (n) and step (a) synchronously;
(n) end data receiving.
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Accused Products
Abstract
A high-power induction-type power supply system includes a supplying-end module consisting of a supplying-end microprocessor, a power driver unit, a signal analysis circuit, a coil voltage detection circuit, a display unit, a power supplying unit, a resonant circuit, a supplying-end coil and a shunt resistor unit, and a receiving-end module consisting of a receiving-end microprocessor, a voltage detection circuit, a rectifier and filter circuit, an amplitude modulation circuit, a protection circuit breaker, a voltage stabilizer circuit, a DC-DC buck converter, a resonant circuit and a receiving-end coil. Subject to time series arrangement, the high-power induction-type power supply system allows transmission of data signal in a stable manner during a charging operation, assuring system operation stability and low power loss. By means of bi-phase decoding, data code is accurately decoded when the receiving-end module is at full load, ensuring system operating reliability.
32 Citations
14 Claims
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1. A bi-phase data signal decoding method used in a high-power induction-type power supply system consisting of a supplying-end module and a receiving-end module for decoding a data code of a data signal, comprising steps of:
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(a) set a built-in forward phase comparator and a built-in reverse phase comparator of a supplying-end microprocessor of the supplying-end module to initialize interruption data analysis and to clear register data; (b) wait for an interruption triggering; (c) determine whether or not the interruption triggered, and then proceed to step (e) when positive or step (d) when negative; (d) determine whether or not a maximum data length counter is overflow, and then return to step (a) when positive or step (b) when negative; (e) judge a phase to be a forward phase or a reverse phase, and then proceed to step (f) when the forward phase is judged, or step (g) when the reverse phase is judged; (f) a first trigger is judged to be a forward phase, thus, set to turn off reverse phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (f) to be a forward phase triggering until that a new setting is made, and then proceed to step (h); (g) the first trigger is judged to be a reverse phase, thus set to turn off forward phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (g) to be a reverse phase triggering until that a new setting is made, and then proceed to step (h); (h) check a signal length to be in match with a set length or not, and then proceed to step (i) when positive or step (j) when negative; (i) the signal length is checked in match with the set length, thus, set bit data and then proceed to step (k); (j) the signal length is checked not in match with the set length, thus, a signal is determined to be a noise, and then clear existing data and re-set to return to step (a); (k) check whether or not a set number of bits has been received, and then proceed to step (l) when negative or step (m) when positive; (l) receiving of the set number of bits is not completed, thus, wait for a next interruption triggering and then return to step (c); (m) the set number of bits has been completely received, thus, set data into a data register, and then initialize a built-in data analysis program and then run step (n) and step (a) synchronously; (n) end data receiving. - View Dependent Claims (2, 3, 4)
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5. A high-power induction-type power supply system comprising a supplying-end module and a receiving-end module, wherein:
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said supplying-end module comprises a supplying-end microprocessor having built therein a forward phase comparator and a reverse phase comparator, a power driver unit, a signal analysis circuit, a coil voltage detection circuit, a display unit, a power supplying unit, a resonant circuit, a supplying-end coil and a shunt resistor unit, said power driver unit, said signal analysis circuit, said coil voltage detection circuit, said display unit, said power supplying unit and said shunt resistor unit being respectively electrically coupled to said supplying-end microprocessor, said supplying-end coil being electrically coupled with said resonant circuit and adapted for transmitting power supply and data signal to said receiving-end module wirelessly; said receiving-end module comprises a receiving-end microprocessor, a voltage detection circuit, a rectifier and filter circuit, an amplitude modulation circuit, a protection circuit breaker, a voltage stabilizer circuit, a DC-DC buck converter, a resonant circuit and a receiving-end coil, said voltage detection circuit, said rectifier and filter circuit, said amplitude modulation circuit, said protection circuit breaker, said voltage stabilizer circuit and said DC-DC buck converter being respectively electrically coupled with said receiving-end microprocessor, said rectifier and filter circuit, said protection circuit breaker and said DC-DC buck converter being electrically connected in series, said receiving-end resonant circuit and said receiving-end coil being electrically connected in parallel to said rectifier and filter circuit and electrically connected with said amplitude modulation circuit in series, said voltage detection circuit, said protection circuit breaker, said voltage stabilizer circuit and said DC-DC buck converter being respectively electrically coupled with said rectifier and filter circuit, said rectifier and filter circuit and said amplitude modulation circuit being respectively electrically coupled with said receiving-end resonant circuit, which is electrically coupled with said receiving-end coil. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification