Lateral diffusion field effect transistor with drain region self-aligned to gate electrode

• US 8,946,013 B2
• Filed: 02/02/2012
• Issued: 02/03/2015
• Est. Priority Date: 04/17/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Feilchenfeld, Natalie B., Gambino, Jeffrey P., Liu, Xuefeng, Voegeli, Benjamin T., Voldman, Steven H., Zierak, Michael J.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/364,663
• Publication Number:
  US 20120126319A1
• Time in Patent Office: 1,097 Days
• Field of Search: 438/183, 438/286, 438/336
• US Class Current: 438/183
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Claims

1. A method manufacturing a semiconductor structure comprising:

forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;

forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;

forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion;

forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein said drain region is formed while said disposable conductive portion is present on said semiconductor substrate and an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion;

removing said disposable conductive portion, while preserving said gate electrode; and

wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.

2. The method of claim 1, wherein a lateral distance between said gate electrode and said disposable conductive portion is less than twice a lateral width of said first portion as measured at a bottom of said first portion.

3. The method of claim 1, further comprising lithographically masking said gate electrode with a photoresist, while exposing said disposable conductive portion.

4. The method of claim 3, further comprising forming a drift region underneath an opening formed by removal of said disposable conductive portion by implanting dopant ions into said opening.

5. The method of claim 4, further comprising forming a first conductivity type well having a doping of a first conductivity type underneath a source side edge of said gate electrode in said semiconductor substrate, wherein said first conductivity type well abuts said gate dielectric, wherein said source region is formed in said first conductivity type well and has a doping of said second conductivity type, wherein said drift region has a doping of a second conductivity type which is the opposite of said first conductivity type, wherein said drift region laterally abuts said drain region, and wherein said source region and said drain region have a doping of said second conductivity type.

6. The method of claim 5, further comprising forming a substrate contact semiconductor region having a doping of said first conductivity type in said semiconductor substrate, wherein said substrate contact semiconductor region laterally abuts said source region.

7. The method of claim 1, wherein said drain region is formed outside of an area occupied by said disposable conductive portion.

8. The method of claim 1, further comprising forming a drift region having a doping of a same conductivity type as said drain region within a surface portion of said semiconductor substrate by implanting dopants through an opening formed by removal of said disposable conductive portion, said drift region laterally contacting said drain region.

9. A method manufacturing a semiconductor structure comprising:

forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;

forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;

forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion;

forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein said drain region is formed outside of an area occupied by said disposable conductive portion and an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion;

removing said disposable conductive portion, while preserving said gate electrode; and

wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.

10. The method of claim 9, wherein a lateral distance between said gate electrode and said disposable conductive portion is less than twice a lateral width of said first portion as measured at a bottom of said first portion.

11. The method of claim 9, wherein said drain region is formed while said disposable conductive portion is present on said semiconductor substrate.

12. The method of claim 9, further comprising forming a drift region having a doping of a same conductivity type as said drain region within a surface portion of said semiconductor substrate by implanting dopants through an opening formed by removal of said disposable conductive portion, said drift region laterally contacting said drain region.

13. The method of claim 12, further comprising forming a first conductivity type well having a doping of a first conductivity type underneath a source side edge of said gate electrode in said semiconductor substrate, wherein said first conductivity type well abuts said gate dielectric, wherein said source region is formed in said first conductivity type well and has a doping of said second conductivity type, wherein said drift region has a doping of a second conductivity type which is the opposite of said first conductivity type, wherein said drift region laterally abuts said drain region, and wherein said source region and said drain region have a doping of said second conductivity type.

14. A method manufacturing a semiconductor structure comprising:

forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;

forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;

forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion;

forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein said drain region is formed while said disposable conductive portion is present on said semiconductor substrate and an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion;

removing said disposable conductive portion, while preserving said gate electrode;

forming a drift region having a doping of a same conductivity type as said drain region within a surface portion of said semiconductor substrate by implanting dopants through an opening formed by removal of said disposable conductive portion, said drift region laterally contacting said drain region; and

wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.

15. The method of claim 14, wherein a lateral distance between said gate electrode and said disposable conductive portion is less than twice a lateral width of said first portion as measured at a bottom of said first portion.

16. The method of claim 14, wherein said drain region is formed outside of an area occupied by said disposable conductive portion.

17. The method of claim 14, further comprising forming a first conductivity type well having a doping of a first conductivity type underneath a source side edge of said gate electrode in said semiconductor substrate, wherein said first conductivity type well abuts said gate dielectric, wherein said source region is formed in said first conductivity type well and has a doping of said second conductivity type, wherein said drift region has a doping of a second conductivity type which is the opposite of said first conductivity type, wherein said drift region laterally abuts said drain region, and wherein said source region and said drain region have a doping of said second conductivity type.