Memory device and signal processing circuit
First Claim
1. A semiconductor device comprising:
- a memory circuit comprising a first transistor and a capacitor;
a logic circuit comprising a second transistor, a third transistor, a fourth transistor, and a fifth transistor; and
a control circuit comprising a sixth transistor and a seventh transistor,wherein a first terminal of the first transistor is electrically connected to one electrode of the capacitor,wherein a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the sixth transistor,wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor,wherein the first terminal of the sixth transistor is directly connected to the first terminal of the seventh transistor,wherein a second terminal of the sixth transistor is directly connected to a second terminal of the seventh transistor,wherein a second terminal of the third transistor is electrically connected to a first terminal of the fifth transistor, andwherein a gate of the second transistor and a gate of the third transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a memory circuit comprising a first transistor and a capacitor; a logic circuit comprising a second transistor, a third transistor, a fourth transistor, and a fifth transistor; and a control circuit comprising a sixth transistor and a seventh transistor, wherein a first terminal of the first transistor is electrically connected to one electrode of the capacitor, wherein a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the sixth transistor, wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor, a first terminal of the sixth transistor, and a first terminal of the seventh transistor, wherein the first terminal of the sixth transistor is directly connected to the first terminal of the seventh transistor, wherein a second terminal of the sixth transistor is directly connected to a second terminal of the seventh transistor, wherein a second terminal of the third transistor is electrically connected to a first terminal of the fifth transistor, and wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first memory circuit comprising a first transistor and a first capacitor; a second memory circuit comprising a second transistor and a second capacitor; a logic circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a first control circuit comprising a seventh transistor and an eighth transistor; a second control circuit comprising a ninth transistor and a tenth transistor; and a precharge circuit, wherein a first terminal of the first transistor is electrically connected to one electrode of the first capacitor, wherein a first terminal of the second transistor is electrically connected to one electrode of the second capacitor, wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor, a first terminal of the fourth transistor, a gate of the fifth transistor, a gate of the sixth transistor, a gate of the seventh transistor, a gate of the ninth transistor, and a first terminal of the precharge circuit, wherein a second terminal of the second transistor is electrically connected to a first terminal of the fifth transistor, a first terminal of the sixth transistor, a gate of the third transistor, a gate of the fourth transistor, a gate of the eighth transistor, a gate of the tenth transistor, and a second terminal of the precharge circuit, wherein a first terminal of the seventh transistor is directly connected to a first terminal of the eighth transistor, wherein a second terminal of the seventh transistor is directly connected to a second terminal of the eighth transistor, wherein a first terminal of the ninth transistor is directly connected to a first terminal of the tenth transistor, wherein a second terminal of the ninth transistor is directly connected to a second terminal of the tenth transistor, wherein the first terminal of the seventh transistor and the first terminal of the eighth transistor are electrically connected to a second terminal of the third transistor and a second terminal of the fifth transistor, and wherein the first terminal of the ninth transistor and the first terminal of the tenth transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the sixth transistor. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. (Withdrawn -Currently Amended) A semiconductor device comprising:
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a first memory circuit comprising a first transistor and a first capacitor; a second memory circuit comprising a second transistor and a second capacitor; a logic circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a first control circuit comprising a seventh transistor and an eighth transistor; a second control circuit comprising a ninth transistor and a tenth transistor; a precharge circuit; a first switch; and a second switch, wherein a first terminal of the first transistor is electrically connected to one electrode of the first capacitor, wherein a first terminal of the second transistor is electrically connected to one electrode of the second capacitor, wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor, a first terminal of the fourth transistor, a gate of the fifth transistor, a gate of the sixth transistor, a gate of the seventh transistor, a gate of the ninth transistor, and a first terminal of the first switch, wherein a second terminal of the second transistor is electrically connected to a first terminal of the fifth transistor, a first terminal of the sixth transistor, a gate of the third transistor, a gate of the fourth transistor, a gate of the eighth transistor, a gate of the tenth transistor, and a first terminal of the second switch, wherein a second terminal of the first switch is electrically connected to a first terminal of the precharge circuit, wherein a second terminal of the second switch is electrically connected to a second terminal of the precharge circuit, wherein a first terminal of the seventh transistor is directly connected to a first terminal of the eighth transistor, wherein a second terminal of the seventh transistor is directly connected to a second terminal of the fourth eighth transistor, wherein a first terminal of the ninth transistor is directly connected to a first terminal of the tenth transistor, wherein a second terminal of the ninth transistor is directly connected to a second terminal of the tenth transistor, wherein the first terminal of the seventh transistor and the first terminal of the eighth transistor are electrically connected to a second terminal of the third transistor and a second terminal of the fifth transistor, and wherein the first terminal of the ninth transistor and the first terminal of the tenth transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the sixth transistor. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification